LTC4253 datasheet(18/34 Pages) LINER

18 / 34 page

LTC4253/LTC4253A

425353afe

APPLICATIONS INFORMATION

POWER GOOD SEQUENCING

After the initial TIMER cycle, GATE ramps up to turn on

the external MOSFET which in turn pulls DRAIN low.

When GATE is within 2.8V of VIN and DRAIN is lower than

VDRNL,thepowergoodsequencestartswithPWRGD1pull-

ing active low. This starts off a 5μA pull-up on the SQTIMER

pin which ramps up until it reaches the 4V threshold then

pulls low. When the SQTIMER pin floats, this delay tSQT is

about 300μs. Connecting an external capacitor CSQ from

SQTIMER to VEE modifies the delay to:

SQT =

4V • C

μA

(5)

PWRGD2 asserts when EN2 goes high and PWRGD1 has

asserted for more than one tSQT. When PWRGD2 suc-

cessfully pulls low, SQTIMER ramps up on another delay

cycle. PWRGD3 asserts when EN2 and EN3 go high and

PWRGD2 has asserted for more than one tSQT.

All three PWRGD signals are reset in UVLO, in UV condi-

tion, if RESET is high or when CT charges up to 4V. In

addition, PWRGD2 is reset by EN2 going low. PWRGD3 is

reset by EN2 or EN3 going low. An overvoltage condition

has no effect on the PWRGD flags. A 50μA current pulls

each PWRGD pin high when reset. As power modules

signal common are different from PWRGD, optoisolation

is recommended. These three pins can sink an optodiode

current. Figure 17 shows an NPN configuration for the

PWRGD interface. A limiting base resistor should be used

for each NPN and the module enable input should have

protection from negative bias current.

SOFT-START

Soft-start is effective in limiting the inrush current during

GATE start-up. Unduly long soft-start intervals can exceed

the MOSFET’s SOA duration if powering-up into an active

load. When the SS pin floats, an internal current source

ramps SS from 0V to 2.2V in about 300μs (0V to 1.4V in

about 200μs for the LTC4253A). Connecting an external

capacitor, CSS, from SS to ground modifies the ramp to

approximate an RC response of:

VSS(t) ≈ VSS 1− e

–t

SSC SS

⎛

⎝

⎜

⎞

⎠

⎟

(6)

An internal resistor divider (95k/5k for the LTC4253 and

47.5k/2.5k for the LTC4253A) scales VSS(t) down by 20

times to give the analog current limit threshold:

ACL (t) =

SS(t)

–V

(7)

This allows the inrush current to be limited to VACL(t)/RS.

The offset voltage, VOS (10mV), ensures CSS is sufficiently

discharged and the ACL amplifier is in current limit mode

before GATE start-up. SS is discharged low during UVLO

at VIN , UV, OV, during the initial timing cycle, a latched

circuit breaker fault or the RESET pin going high.

GATE

GATE is pulled low to VEE under any of the following condi-

tions: in UVLO, when RESET pulls high, in an undervoltage

condition, in an overvoltage condition, during the initial

timing cycle or a latched circuit breaker fault. When GATE

turns on, a 50μA current source charges the MOSFET gate

and any associated external capacitance. VIN limits the

gate drive to no more than 14.5V.

Gate-drain capacitance (CGD) feedthrough at the first

abrupt application of power can cause a gate-source

voltage sufficient to turn on the MOSFET. A unique circuit

pulls GATE low with practically no usable voltage at VIN

and eliminates current spikes at insertion. A large external

gate-source capacitor is thus unnecessary for the purpose

of compensating CGD. Instead, a smaller value (≥10nF)

capacitor CC is adequate. CC also provides compensation

for the analog current limit loop.

GATE has two comparators: the GATE low comparator looks

for <0.5V threshold prior to initial timing; the GATE high

comparator looks for <2.8V relative to VIN and, together

with DRAIN low comparator, sets PWRGD1 output during

GATE start-up.

LTC4253 датащи(PDF) 18 Page - Linear Technology

LTC4253 датащи(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL