LTC2255 datasheet(14/24 Pages) LINER

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LTC2201

2201f

the new sample is small, the charging glitch seen at the

input will be small. If the input change is large, such as

the change seen with input frequencies near Nyquist, then

a larger charging glitch will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential

drive to achieve speciﬁed performance. Each input may

swing ±0.625V for the 2.5V range (PGA = 0) or ±0.417V

for the 1.667V range (PGA = 1), around a common mode

voltage of 1.25V. The VCM output pin (Pin 2) is designed

to provide the common mode bias level. VCM can be tied

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The VCM pin must be bypassed to ground

close to the ADC with 2.2μF or greater.

Input Drive Impedence

As with all high performance, high speed ADCs the dy-

namic performance of the LTC2201 can be inﬂuenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and input reac-

tance can inﬂuence SFDR. At the rising edge of CLK the

sample and hold circuit will connect the 9.1pF sampling

capacitor to the input pin and start the sampling period.

The sampling period ends when CLK falls, holding the

sampled input on the sampling capacitor. Ideally, the

input circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

1/(2FCLK); however, this is not always possible and the

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

INPUT DRIVE CIRCUITS

Figure 3 shows the LTC2201 being driven by an RF trans-

former with a center-tapped secondary. The secondary

center tap is DC biased with VCM, setting the ADC input

signal at its optimum DC level. Figure 3 shows a 1:1 turns

ratio transformer. Other turns ratios can be used; however,

as the turns ratio increases so does the impedance seen by

the ADC. Source impedance greater than 50Ω can reduce

the input bandwidth and increase high frequency distor-

tion. A disadvantage of using a transformer is the loss of

low frequency response. Most small RF transformers have

poor performance at frequencies below 1MHz.

Figure 3. Single-Ended to Differential Conversion

Using a Transformer. Recommended for Input

Frequencies from 1MHz to 100MHz

LTC2201

ANALOG

INPUT

T1 = COILCRAFT WBCI-IT OR

MA/COM ETC1-1T.

RESISTORS, CAPACITORS ARE

0402 PACKAGE SIZE, EXCEPT 2.2μF.

2201 F03

0.1μF

2.2μF

12pF

0.1μF

1:1

25Ω

VCM

AIN+

AIN–

Figure 4. Using a Transmission Line Balun Transformer.

Recommended for Input Frequencies from 50MHz to 250MHz

0.1μF

AIN

–

4.7pF

2.2μF

4.7pF

VCM

ANALOG

INPUT

0.1μF

1:1

T1 = MA/COM ETC1-1-13.

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE,

EXCEPT 2.2μF.

2201 F04

25Ω

10Ω

25Ω

LTC2201

Center-tapped transformers provide a convenient means

of DC biasing the secondary; however, they often show

poor balance at high input frequencies, resulting in large

2nd order harmonics.

Figure 4 shows transformer coupling using a transmis-

sion line balun transformer. This type of transformer has

much better high frequency response and balance than ﬂux

coupled center tap transformers. Coupling capacitors are

added at the ground and input primary terminals to allow

the secondary terminals to be biased at 1.25V.

APPLICATIONS INFORMATION

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