LTC2255 datasheet(13/24 Pages) LINER

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LTC2201

2201f

CONVERTER OPERATION

The LTC2201 is a CMOS pipelined multistep converter

with a front-end PGA. As shown in Figure 1, the converter

has ﬁve pipelined ADC stages; a sampled analog input

will result in a digitized value seven cycles later (see the

Timing Diagram section). The analog input is differential for

improved common mode noise immunity and to maximize

the input range. Additionally, the differential input drive

will reduce even order harmonics of the sample-and-hold

circuit.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage ampliﬁer. In op-

eration, the ADC quantizes the input to the stage and the

quantized value is subtracted from the input by the DAC

to produce a residue. The residue is ampliﬁed and output

by the residue ampliﬁer. Successive stages operate out of

phase so that when odd stages are outputting their residue,

the even stages are acquiring that residue and vice versa.

The phase of operation is determined by the state of the

CLK input pin.

When CLK is high, the analog input is sampled differen-

tially directly onto the input sample-and-hold capacitors,

inside the “input S/H” shown in the block diagram. At the

instant that CLK transitions from high to low, the voltage

on the sample capacitors is held. While CLK is low, the

held input voltage is buffered by the S/H ampliﬁer which

drives the ﬁrst pipelined ADC stage. The ﬁrst stage acquires

the output of the S/H ampliﬁer during the low phase of

CLK. When CLK goes back high, the ﬁrst stage produces

its residue which is acquired by the second stage. At the

same time, the input S/H goes back to acquiring the analog

input. When CLK goes low, the second stage produces its

residue which is acquired by the third stage. An identi-

cal process is repeated for the third and fourth stages,

resulting in a fourth stage residue that is sent to the ﬁfth

stage for ﬁnal evaluation.

Each ADC stage following the ﬁrst has additional range to

accommodate ﬂash and ampliﬁer offset errors. Results

from all of the ADC stages are digitally delayed such that

the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2201 CMOS

differential sample and hold. The differential analog inputs

are sampled directly onto sampling capacitors (CSAMPLE)

through NMOS transitors. The capacitors shown attached

to each input (CPARASITIC) are the summation of all other

capacitance associated with each input.

Figure 2. Equivalent Input Circuit

LTC2201

CLK

2201 F02

VDD

RPARASITIC

3Ω

RPARASITIC

3Ω

AIN+

AIN–

CPARASITIC

1.4pF

CPARASITIC

1.4pF

CSAMPLE

9.1pF

CSAMPLE

9.1pF

RON

20Ω

RON

20Ω

APPLICATIONS INFORMATION

During the sample phase when CLK is high, the NMOS

transistors connect the analog inputs to the sampling

capacitors and they charge to, and track the differential

input voltage. When CLK transitions from high to low, the

sampled input voltage is held on the sampling capacitors.

During the hold phase when CLK is high, the sampling

capacitors are disconnected from the input and the held

voltage is passed to the ADC core for processing. As CLK

transitions from low to high, the inputs are reconnected to

the sampling capacitors to acquire a new sample. Since

the sampling capacitors still hold the previous sample,

a charging glitch proportional to the change in voltage

between samples will be seen at this time at the input of

the converter. If the change between the last sample and

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