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DM9621 датащи(PDF) 17 Page - Davicom Semiconductor, Inc.

номер детали DM9621
подробное описание детали  USB2.0 to 10/100M Fast Ethernet Controller
PDF  66 Pages
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производитель  DAVICOM [Davicom Semiconductor, Inc.]
домашняя страница  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9621 датащи(HTML) 17 Page - Davicom Semiconductor, Inc.

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DM9621
USB2.0 to Fast Ethernet Controller
Preliminary
17
Version: DM9621 -14-DS-P02
February 23, 2011
4.5 RX Status Register ( 06H )
Bit
Name
Default
Description
7
RF
PHS0,RO
Runt Frame
It is set to indicate the received frame has the size smaller than 64 bytes.
6
MF
PHS0,RO
Multicast Frame
It is set to indicate the received frame has a multicast address.
5
LCS
PHS0,RO
Late Collision Seen
It is set to indicate a late collision found during the frame reception.
4
RWTO
PHS0,RO
Receive Watchdog Time-Out
It is set to indicate receive more than 2048 bytes.
3
PLE
PHS0,RO
Physical Layer Error
It is set to indicate a physical layer error found during the frame reception.
2
AE
PHS0,RO
Alignment Error
It is set to indicate the received frame ends with a non-byte boundary.
1
CE
PHS0,RO
CRC Error
It is set to indicate the received frame ends with a CRC error.
0
FOE
PHS0,RO
FIFO Overflow Error
It is set to indicate a FIFO Overflow error happens during the frame reception.
4.6 Receive Overflow Counter Register ( 07H )
This register can be cleared by writing any data this byte. Or they also can be cleared by read this byte if register 0H bit 5 is 0”.
Bit
Name
Default
Description
7
RXFU
PHS0,RW/C
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition.
6:0
ROC
PHS0,RW/C
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO
overflow.



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