ADP1879ACPZ-0.6-R7 datasheet(18/40 Pages) AD

18 / 40 page

ADP1878/ADP1879

Data Sheet

Rev. A | Page 18 of 40

STARTUP

Each ADP1878/ADP1879 has an internal regulator (VREG)

for biasing and supplying power for the integrated N-channel

MOSFET drivers. Place a bypass capacitor directly across the

VREG (Pin 7) and PGND (Pin 13) pins. Included in the power-

up sequence is the biasing of the current sense amplifier, the

current sense gain circuit (see the Programming Resistor (RES)

Detect Circuit section), the soft start circuit, and the error

amplifier.

The current sense blocks provide valley current information

(see the Programming Resistor (RES) Detect Circuit section)

and they are a variable of the compensation equation for loop

stability (see the Compensation Network section). In a process

performed by the RES detect circuit, the valley current informa-

tion is extracted by forcing 0.4 V across the RES and PGND pins

generating current. The current through the RES resistor is used

to set the current sense amplifier gain (see the Programming

Resistor (RES) Detect Circuit section). This process takes approx-

imately 800 μs, after which time the drive signal pulses appear at

the DRVL and DRVH pins synchronously, and the output voltage

begins to rise in a controlled manner through the soft start

sequence.

The soft start and error amplifier blocks determine the rise time

of the output voltage (see the Soft Start section). At the beginning

of a soft start, the error amplifier charges the external compensa-

tion capacitor, causing the COMP pin to rise (see Figure 65).

Tying the VREG pin to the EN pin via a pull-up resistor causes

the voltage at the EN pin to rise above the enable threshold of

630 mV, thereby enabling the ADP1878/ADP1879.

Figure 65. COMP Voltage Range

SOFT START

The ADP1878 employs externally programmable, soft start

circuitry that charges up a capacitor tied to the SS pin to GND.

This prevents input inrush current through the external MOSFET

from the input supply (VIN). The output tracks the ramping voltage

by producing PWM output pulses to the high-side MOSFET. The

purpose is to limit the inrush current from the high voltage

input supply (VIN) to the output (VOUT).

PRECISION ENABLE CIRCUITRY

The ADP1878/ADP1879 have precision enable circuitry. The

precision enable threshold is 630 mV including 30 mV of

hysteresis (see Figure 66). Connecting the EN pin to GND

disables the ADP1878/ADP1879, reducing the supply current

of the device to approximately 140 μA.

Figure 66. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the

ADP1878/ADP1879

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) feature prevents the device

from operating both the high- and low-side N-channel MOSFETs

at extremely low or undefined input voltage (VIN) ranges.

Operation at an undefined bias voltage can result in the

incorrect propagation of signals to the high-side power switches.

This, in turn, results in invalid output behavior that can cause

damage to the output devices, ultimately destroying the device

tied at the output. The UVLO level is set at 2.65 V (nominal).

ON-BOARD LOW DROPOUT (LDO) REGULATOR

The ADP1878/ADP1879 use an on-board LDO to bias the

internal digital and analog circuitry. With proper bypass

capacitors connected to the VREG pin (output of the internal

LDO), this pin also provides power for the internal MOSFET

drivers. It is recommended to float VREG if VIN is used for

greater than 5.5 V operation. The minimum voltage at which

bias is guaranteed to operate is 2.75 V at VREG (see Figure 67).

Figure 67. On-Board Regulator

For applications where VIN is decoupled from VREG, the

minimum voltage at VIN must be 2.9 V. It is recommended to tie

VIN and VREG together if the VIN pin is subjected to a 2.75 V rail.

COMP

>2.4V

2.4V

1.0V

500mV

HICCUP MODE INITIALIZED

MAXIMUM CURRENT (UPPER CLAMP)

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START

PERIOD IF CONTINUOUS CONDUCTION

MODE OF OPERATION IS SELECTED.

LOWER CLAMP

PRECISION

ENABLE COMP.

TO ENABLE

ALL BLOCKS

630mV

VREG

10kΩ

REF

VREG

VIN

ON-BOARD REGULATOR

ADP1879ACPZ-0.6-R7 датащи(PDF) 18 Page - Analog Devices

ADP1879ACPZ-0.6-R7 датащи(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL