ADP1048ARQZ-R7 datasheet(14/84 Pages) AD

14 / 84 page

ADP1047/ADP1048

Data Sheet

Rev. 0 | Page 14 of 84

CURRENT BALANCING (IBAL PIN, ADP1048 ONLY)

The ADP1048 has a dedicated circuit to maintain current balance

in each interleaved phase when operating in interleaved PFC

topology. This ensures that each interleaved phase provides equal

power regardless of the tolerance of the inductor and the boost

switch driving circuitry.

The input is through the IBAL pin specifically provided for the

ADP1048. The current balancing circuit monitors the current

flowing in both switches of the interleaved PFC topology and

stores this information. It compensates the PWM signals,

ensuring equal current flow to balance the current between

interleaved phases. Several switching cycles are required for

the circuit to operate effectively. The current balance settings

are programmed in Register 0xFE43 and Register 0xFE95.

IBAL

PWM

PWM2

PGND

ADP1048

0° TO 180°

180° TO 360°

OUTPUT OF PFC

CURRENT LOOP

–

ADC

PWM

Figure 10. Current Balancing (IBAL) for the ADP1048

VOLTAGE SENSE

Voltage sensing is used for the control, protection, and monitor-

ing of the PFC stage. Input and output voltages are sensed using

dedicated ADCs and references (see Figure 11).

ADP1047/ADP1048

VAC

PGND

VFB

VOUT

VREC

ADC

11-BIT

+ –

ADC

11-BIT

+ –

DAC

7-BIT

OVP

OLP

OVP

Figure 11. Typical Voltage Sense Configuration

The voltage sense can be calibrated digitally to remove any

errors due to external components (see the Output Voltage

(VFB) Calibration and Trim section). This calibration can

be performed in the production environment; the settings

are saved in the EEPROM of the ADP1047/ADP1048.

Input Voltage Sensing (VAC Pin)

The VAC pin is used for the monitoring and protection of the

rectified power supply input voltage. The sense point on the

power rail requires an external resistor divider to bring the signal

within the operating input range of the ADC (0 V to 1.6 V).

This scaled-down signal is fed into a high speed Σ-Δ ADC.

The output of the Σ-Δ ADC goes to the digital filter and is used

for the following purposes:

•

The output is decimated at the switching frequency for the

control loop. The effective number of bits (ENOB) is >7

when the current loop bandwidth is 10 kHz; the ENOB

is >10 when the current loop bandwidth is 1 kHz.

•

The 11-bit result is calculated and updated at each half line

cycle for high accuracy input voltage and power monitoring.

Output Voltage Sensing (VFB Pin)

The VFB pin is used for the control, monitoring, and protection

of the output voltage. This voltage is the main feedback loop for

the power supply control loop. The sense point on the power rail

requires an external resistor divider to bring the signal within the

operating input range of the ADC (0 V to 1.6 V). This scaled-

down signal is fed into a high speed Σ-Δ ADC.

The output of the Σ-Δ ADC goes to the digital filter and is used

for the following purposes:

•

The 11-bit result is used at each half line cycle for the

normal control loop to control the value of the output

voltage.

•

The 10-bit, 1.5 kHz update rate is used for the fast voltage

control loop to control the value of the output voltage

during large transients.

To reduce the current distortion from the output voltage feed-

back, a prefilter is implemented before the voltage loop filter.

The prefilter detects the zero-crossing point of the input voltage

to identify the half input line cycle. The prefilter then performs

an averaging function for the sampled VFB signal during this

half line cycle. In this way, the fundamental frequency of the

output bulk voltage ripple and its harmonics are significantly

attenuated.

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