ADP1048ARQZ-R7 datasheet(76/84 Pages) AD

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ADP1047/ADP1048

Data Sheet

Rev. 0 | Page 76 of 84

SMART VOUT LOW LINE (VOL1) REGISTER

Table 131. Register 0xFE46—Smart VOUT Low Line (VOL1)

Bits

Bit Name

R/W

Description

[15:11]

RSVD

Reserved.

[10:0]

VOL1

R/W

These bits set the output voltage under low power mode operation with low line input.

SMART VOUT LOW LINE (VOL2) REGISTER

Table 132. Register 0xFE47—Smart VOUT Low Line (VOL2)

Bits

Bit Name

R/W

Description

[15:11]

RSVD

Reserved.

[10:0]

VOL2

R/W

These bits set the output voltage under high power mode operation with low line input.

SMART VOUT HIGH LINE (VOH1) REGISTER

Table 133. Register 0xFE48—Smart VOUT High Line (VOH1)

Bits

Bit Name

R/W

Description

[15:11]

RSVD

Reserved.

[10:0]

VOH1

R/W

These bits set the output voltage under low power mode operation with high line input.

SMART VOUT HIGH LINE (VOH2) REGISTER

Table 134. Register 0xFE49—Smart VOUT High Line (VOH2)

Bits

Bit Name

R/W

Description

[15:11]

RSVD

Reserved.

[10:0]

VOH2

R/W

These bits set the output voltage under high power mode operation with high line input.

SMART VOUT UPPER LIMIT (VOH) REGISTER

Table 135. Register 0xFE4A—Smart VOUT Upper Limit (VOH)

Bits

Bit Name

R/W

Description

[15:11]

RSVD

Reserved.

[10:0]

VOH

R/W

These bits set the output voltage when the VAC input voltage is higher than the value set in

SMART VOUT SUPER HIGH LINE REGISTER

Table 136. Register 0xFE4B—Smart VOUT Super High Line

Bits

Bit Name

R/W

Description

[15:11]

RSVD

Reserved.

[10:0]

Super high line

voltage

R/W

These bits set the input voltage value as a super high line limit.

SYNC DELAY REGISTER

Table 137. Register 0xFE4C—SYNC Delay

Bits

Bit Name

R/W

Description

[15:0]

tSYNC_DELAY

R/W

These bits set the additional delay between the external synchronization reference clock signal

and the rising edge of PWM. Each LSB corresponds to 80 ns resolution.

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