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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADP1046ACPZ-R7 датащи(PDF) 8 Page - Analog Devices |
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ADP1046ACPZ-R7 датащи(HTML) 8 Page - Analog Devices |
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8 / 96 page  ADP1046 Data Sheet Rev. 0 | Page 8 of 96 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Measurement Accuracy Factory trimmed at 1 V 0 mV to 160 mV −0.5 +0.5 % FSR −8 +8 mV 0% to 100% of usable input voltage range −3.0 +3.0 % FSR −42 +42 mV Temperature Readings According to Internal Linearization Scheme RTD source set to 46 μA (Register 0x11 set to 0xE6); NTC R0 = 100 kΩ, 1%, beta = 4250, 1%; REXT = 16.5 kΩ, 1% 25°C to 100°C 7 °C 100°C to 125°C 5 °C OTP Threshold Accuracy T = 85°C with 100 kΩ||16.5 kΩ −0.9 +0.25 % FSR −14.4 +4 mV T = 100°C with 100 kΩ||16.5 kΩ −0.5 +1.1 % FSR −8 +17.6 mV Comparator Speed 10.5 ms OTP Threshold Hysteresis 16 mV PGOOD1, PGOOD2, SHAREo PINS (OPEN DRAIN) Output Low Voltage VOL 0.4 V PSON, FLAGIN, SHAREi PINS (DIGITAL INPUTS) Input Low Voltage VIL 0.4 V Input High Voltage VIH VDD − 0.4 V FLAGIN Propagation Delay Does not include debounce time (Register 0x0A[3] = 1); flag action set to disable PSU 200 ns Leakage Current 1.0 μA GATE PIN Output Low Voltage VOL 0.4 V Output High Voltage VOH VDD − 0.4 V SDA/SCL PINS VDD = 3.3 V Input Low Voltage VIL 0.4 V Input High Voltage VIH VDD − 0.4 V Output Low Voltage VOL 0.4 V Leakage Current 1.0 μA SERIAL BUS TIMING See Figure 3 Clock Operating Frequency 10 100 400 kHz Bus-Free Time tBUF Between stop and start conditions 1.3 μs Start Hold Time tHD;STA Hold time after (repeated) start condition; after this period, the first clock is generated 0.6 μs Start Setup Time tSU;STA Repeated start condition setup time 0.6 μs Stop Setup Time tSU;STO 0.6 μs SDA Setup Time tSU;DAT 100 ns SDA Hold Time tHD;DAT For readback 125 ns For write 300 ns SCL Low Timeout tTIMEOUT 25 35 ms SCL Low Period tLOW 1.3 μs SCL High Period tHIGH 0.6 μs Clock Low Extend Time tLO;SEXT 25 ms SCL, SDA Fall Time tF 20 300 ns SCL, SDA Rise Time tR 20 300 ns |
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