AD9653 datasheet(34/40 Pages) AD

34 / 40 page

AD9653

Data Sheet

Rev. 0 | Page 34 of 40

MEMORY MAP REGISTER TABLE

The AD9653 uses a 3-wire interface and 16-bit addressing and,

therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3

and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high,

the SPI enters a soft reset, where all of the user registers revert

to their default values and Bit 2 is automatically cleared.

Table 19.

ADDR

(Hex)

Parameter Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Comments

Chip Configuration Registers

0x00

SPI port

configuration

0 =

SDO

active

LSB first

Soft

reset

1 =

16-bit

address

1 =

16-bit

address

Soft

reset

LSB first

0 = SDO

active

0x18

The nibbles

are mirrored

so that LSB-

first or MSB-

first mode

registers

correctly. The

default for

ADCs is 16-bit

mode.

0x01

Chip ID (global)

8-bit chip ID, Bits[7:0]

AD9653 0xB5 = quad, 16-bit, 125 MSPS serial LVDS

0xB5

Unique chip

ID used to

differentiate

devices; read

only.

0x02

Chip grade

(global)

Open

Speed grade ID[6:4]

110 = 125 MSPS

Open

Unique

speed grade

ID used to

differentiate

graded

devices; read

only.

Device Index and Transfer Registers

0x05

Device index

Open

Clock

Channel

DCO

Clock

Channel

FCO

Data

Channel

Data

Channel

Data

Channel

Data

Channel

0x3F

Bits are set to

determine

which device

on chip

receives the

next write

command.

The default is

all devices on

chip.

0xFF

Transfer

Open

Initiate

override

0x00

Set sample

rate override.

Global ADC Function Registers

0x08

Power modes

(global)

Open

External

power-

down

function

0 = full

power-

down

1 =

standby

Open

Power mode

00 = chip run

01 = full power-

down

10 = standby

11 = reset

0x00

Determines

various

generic

modes of chip

operation.

0x09

Clock (global)

Open

Duty

cycle

stabilize

0 = on

1 = off

0x01

Turns duty

cycle stabilizer

on or off.

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