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AD6672 датащи(PDF) 20 Page - Analog Devices

номер детали AD6672
подробное описание детали  IF Receiver
PDF  32 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD6672 датащи(HTML) 20 Page - Analog Devices

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AD6672
Rev. 0 | Page 20 of 32
DIGITAL OUTPUTS
The AD6672 output drivers can be configured for either ANSI
LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD6672 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the SPI
interface. The data outputs can be three-stated by using the
output enable bar bit (Bit 4) in Register 0x14. This OEB
function is not intended for rapid access to the data bus.
Timing
The AD6672 provides latched data with a pipeline delay of
10 input sample clock cycles when NSR is disabled and provides
13 input sample clock cycles when NSR is enabled. Data outputs
are available one propagation delay (tPD) after the rising edge of
the clock signal.
Minimize the length of the output data lines as well as the loads
placed on these lines to reduce transients within the AD6672.
These transients may degrade converter dynamic performance.
The lowest typical conversion rate of the AD6672 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD6672 also provides the data clock output (DCO)
intended for capturing the data in an external register. Figure 2
shows a timing diagram of the AD6672 output modes.
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock cycles. An overrange at the
input is indicated by this bit 10 clock cycles after it occurs.
Table 10. Output Data Format
Input (V)
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
Offset Binary Output Mode
Twos Complement Mode (Default)
OR
VIN+ − VIN−
<−0.875
000 0000 0000
100 0000 0000
1
VIN+ − VIN−
−0.875
000 0000 0000
100 0000 0000
0
VIN+ − VIN−
0
100 0000 0000
000 0000 0000
0
VIN+ − VIN−
+0.875
111 1111 1111
011 1111 1111
0
VIN+ − VIN−
>+0.875
111 1111 1111
011 1111 1111
1



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