AD6672 datasheet(18/32 Pages) AD

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AD6672

Rev. 0 | Page 18 of 32

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD6672.

The full-scale input range can be adjusted by varying the

reference voltage via SPI. The input span of the ADC tracks

reference voltage changes linearly.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD6672 sample clock inputs,

CLK+ and CLK−, should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or via capacitors. These pins are biased

internally (see Figure 29) and require no external bias. If the

inputs are floated, the CLK− pin is pulled low to prevent

spurious clocking.

AVDD

CLK+

4pF

CLK–

0.9V

Figure 29. Simplified Equivalent Clock Input Circuit

Clock Input Options

The AD6672 has a very flexible clock input structure. Clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter

is of the most concern, as described in the Jitter Considerations

section.

Figure 30 and Figure 31 show two preferable methods for

clocking the AD6672 (at clock rates of up to 625 MHz). A low

jitter clock source is converted from a single-ended signal to a

differential signal using an RF balun or RF transformer.

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 250 MHz. The

back-to-back Schottky diodes across the secondary winding of

the transformer limit clock excursions into the AD6672 to

approximately 0.8 V p-p differential. This limit helps prevent

the large voltage swings of the clock from feeding through to

other portions of the AD6672 while preserving the fast rise and

fall times of the signal, which are critical for low jitter

performance.

390pF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1Z

XFMR

Figure 30. Transformer-Coupled Differential Clock (Up to 250 MHz)

390pF

CLOCK

INPUT

1nF

25Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Figure 31. Balun-Coupled Differential Clock (Up to 625 MHz)

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins as shown in Figure 32. The AD9510, AD9511, AD9512,

AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,

AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/

ADCLK925 clock drivers offer excellent jitter performance.

100Ω

0.1µF

240Ω

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD95xx,

ADCLK9xx

PECL DRIVER

Figure 32. Differential PECL Sample Clock (Up to 625 MHz)

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 33. The AD9510,

AD9511, AD9512, AD9513, AD9514, AD9515, AD9516,

AD9517, AD9518, AD9520, AD9522, AD9523, and AD9524

clock drivers offer excellent jitter performance.

100Ω

0.1µF

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

AD95xx

LVDS DRIVER

ADC

Figure 33. Differential LVDS Sample Clock (Up to 625 MHz)

Input Clock Divider

The AD6672 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. For

divide ratios other than 1, the duty cycle stabilizer (DCS) is

enabled by default on power-up.

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