Q67100-Q2001 datasheet(7/10 Pages) SIEMENS

номер детали	Q67100-Q2001

подробное описание детали	8M x 32-Bit Dynamic RAM Module

PDF	10 Pages

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производитель	SIEMENS [Siemens Semiconductor Group]

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Semiconductor Group

HYM 328020S/GS-50/-60

× 32-Bit

AC Characteristics 5)6)

A = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

min.

max.

min.

max.

common parameters

Random read or write cycle time

–

110

–

RAS precharge time

–

RAS pulse width

RAS

10k

CAS pulse width

CAS

10k

Row address setup time

ASR

0–

0–ns

Row address hold time

tRAH

8–

–ns

Column address setup time

tASC

0–

0–ns

Column address hold time

tCAH

–

RAS to CAS delay time

tRCD

RAS to column address delay time

tRAD

RAS hold time

tRSH

–

CAS hold time

tCSH

–

CAS to RAS precharge time

tCRP

5–

5–ns

Transition time (rise and fall)

Refresh period

tREF

–32

–

Read Cycle

Access time from RAS

RAC

–

8, 9

Access time from CAS

CAC

–

8, 9

Access time from column address

–

8,10

Column address to RAS lead time

RAL

–

Read command setup time

RCS

0–

0–ns

Read command hold time

RCH

0–

0–ns

Read command hold time referenced to

RAS

tRRH

0–

0–ns

CAS to output in low-Z

CLZ

0–

0–ns

Output buffer turn-off delay

OFF

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