2

Precision Edge®

SY58034U

Micrel, Inc.

M9999-082707

hbwhelp@micrel.com or (408) 955-1690

PACKAGE/ORDERING INFORMATION

Package

Operating

Package

Lead

Part Number

Type

Range

Marking

Finish

SY58034UMI

MLF-32

Industrial

SY58034U

Sn-Pb

MLF-32

Industrial

SY58034U

Sn-Pb

MLF-32

Industrial

SY58034U with

NiPdAu

Pb-free bar-line indicator Pb-Free

MLF-32

Industrial

SY58034U with

NiPdAu

Pb-free bar-line indicator Pb-Free

Notes:

2. Tape and Reel.

3. Pb-Free package recommended for new designs.

Pin Number

Pin Name

Pin Function

1, 4

IN0, /IN0

Differential Input: These input pairs are the differential signal inputs to the device. These

5, 8

IN1, /IN1

inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally

terminates to a VT pin through 50ý. Note that these inputs will default to an indeterminate

state if left open. Please refer to the “Input Interface Applications” section for more details.

2, 6

VT0, VT1

Input Termination Center-Tap: Each side of the differential input pair terminates to a VT

pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum

interface flexibility. See “Input Interface Applications” section for more details.

31

SEL

This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note

that this input is internally connected to a 25ký pull-up resistor and will default to a logic

HIGH state if left open. The MUX select switchover function is asynchronous.

10

NC

No connect.

11, 16, 18,

VCC

Positive Power Supply: Bypass with 0.1µF

™™0.01µF low ESR capacitors and place as

23, 25, 30

close to the VCC pins as possible.

29, 28

Q0, /Q0,

Differential Outputs: These CML output pairs are low skew output copies of the selected

27, 26

Q1, /Q1,

input. The output stage is optimized to deliver a 400mV swing (single-ended) into 50ý.

22, 21

Q2, /Q2,

Each output includes a 50ý source-termination resistor, thus minimizing any return

20, 19

Q3, /Q3,

reflections. Unused output pins may be left floating. Please refer to the “Truth Table”

15, 14

Q4, /Q4,

for details.

13, 12

Q5, /Q5

9, 17, 24, 32

GND,

Ground. Ground pin and exposed pad must be connected to the same ground plane.

Exposed Pad

3, 7

VREF-AC0,

VREF-AC1

Due to the limited capability, the VREF-AC pin is only intended to drive its respective VT

pin.

PIN DESCRIPTION

24

23

22

21

20

19

18

17

GND

VCC

Q2

/Q2

Q3

/Q3

VCC

GND

IN0

VT0

VREF-AC0

/IN0

IN1

VT1

VREF-AC1

/IN1

1

2

3

4

5

6

7

8

910 11 12 13 14 15 16

32 31 30 29 28 27 26 25

TRUTH TABLE

SEL

0

IN0 Input Selected

1

IN1 Input Selected