SX8663 datasheet(51/64 Pages) SEMTECH

51 / 64 page

ADVANCED COMMUNICATIONS & SENSING

Rev5 4

th August 2011

www.semtech.com

SX8663

Capacitive Button Matrix (up to 36) and Proximity Controller

with Individual LED Drivers and Buzzer Output

I2C INTERFACE

The I2C implemented on the SX8663 is compliant with:

- standard (100kb/s), fast mode (400kb/s)

- slave mode

- 7 bit address (default 0x2B). The default address can be changed in the NVM at address 0x04.

The host can use the I2C to read and write data at any time. The effective changes will be applied at the next

processing phase (section 3.2).

Three types of registers are considered:

- status (read). These registers give information about the status of the capacitive buttons, GPIs, operation modes

etc…

- control (read/write). These registers control the soft reset, operating modes, GPIOs and offset compensation.

- SPM gateway (read/write). These registers are used for the communication between host and the SPM. The

SPM gateway communication is done typically at power up and is not supposed to be changed when the

application is running. The SPM needs to be re-stored each time the SX8663 is powered down.

The SPM can be stored permanently in the NVM memory of the SX8663. The SPM gateway communication over

the I2C at power up is then not required.

The I2C will be able to read and write from a start address and then perform read or writes sequentially, and the

address increments automatically.

The supported I2C access formats are described in the next sections.

6.1

I2C Write

The format of the I2C write is given in Figure 48.

After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The

SX8663 then acknowledges [A] that it is being addressed, and the master sends an 8 bit Data Byte consisting of

the SX8663 Register Address (RA). The slave acknowledges [A] and the master sends the appropriate 8 bit Data

Byte (WD0). Again the slave acknowledges [A]. In case the master needs to write more data, a succeeding 8 bit

Data Byte will follow (WD1), acknowledged by the slave [A]. This sequence will be repeated until the master

terminates the transfer with the Stop condition [P].

Figure 48

I2C write

The register address is incremented automatically when successive register data (WD1...WDn) is supplied by the

master.

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