SC461 datasheet(27/31 Pages) SEMTECH

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SC461

Applications Information (continued)

A separate ground plane or island should be used

for AGND and all associated components. The

AGND island should avoid overlapping switching

signals on other layers (DH/DL/BST/LX).

Connect PGND and AGND together with a zero

ohm resistor or copper trace. Make the connec-

tion near the AGND and PGND pins of the IC.

Power Components

Use short, wide traces between the following

power components.

Input capacitors and high-side MOSFETs

High-side and Low-side MOSFETs and in-

ductor (LX connection). Use wide copper

traces to provide high current carrying ca-

pacity and for heat dissipation.

Inductor and output capacitors.

All PGND connections — the input capaci-

tors, low-side MOSFETs, output capacitors,

and the PGND pin of the SC461.

An inner layer ground plane is recommended.

Each power component requires a short, low

impedance connection to the PGND plane.

Place vias to the PGND plane directly near the

component pins.

Use short wide traces for the pin connections

from the SC461 (LX, DH, DL and BST). Do not

route these traces near the sensitive low-noise

analog signals (FB, SS, TON, V

OUT).

Avoid overlapping of the DL trace with LX/DH/

BST. This helps reduce transient peaks on the

gate of the low-side MOSFET during the turn-on

of the high-side MOSFET.

Low-noise Analog Circuits

Low-noise analog circuits are sensitive circuits that are

referenced to AGND. Due to their high impedance and

sensitivity to noise, it is important that these circuits be

located as far as possible from the switching signals.

Use a plane or solid area for AGND. Place all

components connected to AGND above this

area.

Use short direct traces for the AGND con-

nections to all components.

Place vias to the AGND plane directly near

the component pins.

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Proper routing of the V

OUT sense trace is essential

since it feeds into the FB resistor divider. Noise

on the FB waveform will cause instability and

multiple pulsing.

Connect the V

OUT sense trace directly to

the output capacitor or a ceramic bypass

capacitor.

Route this trace over to the VOUT pin, care-

fully avoiding all switching signals and

power components.

Route this trace in a quiet layer if possible.

Route this trace away from the switch-

ing traces and components, even if the

trace is longer. Avoid shorter trace routing

through the power switching area.

If a bypass capacitor is used at the IC side

of the V

OUT sense trace, it should be placed

near the FB resistor divider.

All components connected to the FB pin must

be located near the pin. The FB traces should be

kept small and not routed near any noisy switch-

ing connections or power components.

Place the SS capacitor near the SS pin with a

short direct connection to the AGND plane.

Place the R

LIM resistor near the IC. For an accurate

LIM current sense connection, route the RLIM trace

directly to the drain of the low-side MOSFET (LX).

Use an inner routing layer if needed.

Place the R

TON resistor near the TON pin. Route

TON to the TON pin and to AGND using short

traces and avoid all switching signals.

Bypass Capacitors

The device requires bypass capacitors for the following

pins.

VDDA pin with respect to AGND. This 0.1μF

minimum capacitor must be placed and routed

close to the IC pins, on the same layer as the IC.

This capacitor also functions as bypass for the

LDO output, since the VDDA and VLDO pins are

adjacent.

VDDP with respect to PGND. This 1μF minimum

capacitor must be placed and routed close to

the IC pins and on the same layer as the IC.

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