SC461 datasheet(18/31 Pages) SEMTECH

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SC461

After the SS capacitor voltage reaches 1.5V, the SS capaci-

tor continues to charge until the SS voltage is equal to

67% of VDDA. At this time the Power Good monitor com-

pares the FB pin and sets the PGOOD output high (open

drain) if VOUT is in regulation. The time between VOUT

reaching the regulation point and the PGOOD output

going high is shown by the following equation.

The time from the rising edge of the EN pin to the PGOOD

output going high is shown by the following equation.

After the Power Good Start-up Delay Time is completed,

the SS pin is internally pulled up to the VDDA supply.

The soft-start cycle and Power Good timing can be seen in

the Figure 10.

PGOOD

CSS charging

current 3uA

VSS = 1.5V

VOUT in regulation

VSS = 67% × VDDA

tSS

tPGOOD

Figure 10 — Soft-start Cycle and Power Good timing

Pre-Bias Start-up

SC461 can support soft-start with an output pre-bias. The

SS capacitor ramp time is the same as a normal start-up

when the output voltage starts from zero. Under a pre-

bias start-up, the DH and DL drivers inhibit switching until

40% of the ramp at the SS pin equals the pre-bias FB

voltage level. Pre-bias start-up is achieved by turning off

the lower MOSFET when the inductor current reaches zero

during the soft-start cycle. This method helps prevent the

output voltage from decreasing.

Power Good Output

The PGOOD (power good) output is an open-drain output

which requires a pull-up resistor. During start-up, PGOOD

is held low and is not allowed to transition high until the

output voltage is in regulation and the SS pin has reached

67% of VDDA. The time from EN going high to PGOOD

going high is typically 12.5ms for CSS = 10nF and VDDA =

5V. For CSS = 10nF and VDDA = 3V the typical PGOOD

time is 7.5ms.

When the voltage at the FB pin is 10% below the nominal

voltage, PGOOD is pulled low. Once PGOOD pulls low

there is typically 2% hysteresis to prevent chatter on the

PGOOD output.

PGOOD will transition low if the FB voltage exceeds +20%

of nominal (720mV), which is also the over-voltage shut-

down threshold. PGOOD also pulls low if the EN pin is low

and VDDA is present.

Output Over-Voltage Protection

Over-voltage protection (OVP) becomes active as soon as

the device is enabled. The OVP threshold is set at 600mV

+ 20% (720mV). There is a 5μs delay built into the OVP

detector to prevent false transitions. When V

FB exceeds the

OVP threshold, DL is driven high and the low-side MOSFET

is turned on. DL remains high and the controller remains

off. If the FB pin remains above the OVP threshold, DL

remains high and the IC will maintain this maintain this

state with no automatic recovery. If FB falls below the OVP

threshold, the device goes through the automatic fault

recovery cycle. When the automatic recovery cycle is

completed, the device will attempt a new soft-start cycle.

At the start of the soft-start cycle, the DL output will go

low for typically 30us while the controller initializes the

Applications Information (continued)

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