SC401B datasheet(20/32 Pages) SEMTECH

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SC401B

start up process (Figure 8), 40% of the voltage at the SS

pin is used as the reference for the FB comparator. The

PWM comparator issues an on-time pulse when the

voltage at the FB pin is less than 40% of the SS pin. As a

result, the output voltage follows the SS voltage. The

output voltage reaches and maintains regulation when

the soft start voltage is > 1.5V. The time between the first

LX pulse and V

OUT reaching regulation is the soft-start time

SS). The calculation for the soft-start time is shown by the

following equation.

The voltage at the SS pin continues to ramp up and eventu-

ally equals 64% of V

DD. After the soft start completes, the

FB pin voltage is compared to an internal reference of 0.6V.

The delay time between the V

OUT regulation point and

PGOOD going high is shown by the following equation.

)

(

DELAY

PGOOD

Figure 8 — Soft-start Timing Diagram

Pre-Bias Startup

The SC401B can start up normally even when there is an

existing output voltage present. The soft start time is still

the same as normal start up (when the output voltage

starts from zero). The output voltage starts to ramp up

when 40% of the voltage at SS pin meets the existing FB

voltage level. Pre-bias startup is achieved by turning off

the lower gate when the inductor current falls below zero.

This method prevents the output voltage from

discharging.

Power Good Output

The PGOOD (power good) output is an open-drain output

which requires a pull-up resistor. When the voltage at the

FB pin is 10% below the nominal voltage, PGOOD is pulled

low. It is held low until the output voltage returns above

-8% of nominal.

PGOOD will transition low if the V

FB pin exceeds +20% of

nominal, which is also the over-voltage shutdown thresh-

old. PGOOD also pulls low if the EN/PSV pin is low when

VDD is present.

Output Over-Voltage Protection

Over-voltage protection becomes active as soon as the

device is enabled. The threshold is set at 600mV + 20%

(720mV). When V

FB exceeds the OVP threshold, DL latches

high and the low-side MOSFET is turned on. DL remains

high and the controller remains off, until the EN/PSV input

is toggled or VDD is cycled. There is a 5μs delay built into

the OVP detector to prevent false transitions. PGOOD is

also low after an OVP event.

Output Under-Voltage Protection

When V

FB falls 25% below its nominal voltage (falls to

450mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to tri-

state the MOSFETs. The controller stays off until EN/PSV is

toggled or VDD is cycled.

VDD UVLO, and POR

UVLO (Under-Voltage Lock-Out) circuitry inhibits switching

and tri-states the DH/DL drivers until VDD rises above 3V.

An internal POR (Power-On Reset) occurs when VDD

exceeds 3V, which resets the fault latch and a soft-start

counter cycle begins which prepares for soft-start. The

SC401B then begins a soft-start cycle. The PWM will shut

off if VDD falls below 2.4V.

Applications Information (continued)

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