Page Write Sequence

Read Operation

In this mode, the master reads the device data after setting the slave address. Following the R/W bit

(=

²0²) and the acknowledge bit, the register address (An) is written to the address W pointer. Next the

START condition and slave address are repeated followed by the R/W bit (=

²1²). The data which was

addressed is then transmitted. The address pointer is only incremented on reception of an acknowledge

clock. The device will then place the data at address An+1 on the bus. The master reads and

acknowledges the new byte and the address pointer is incremented to

²An+2². After reaching the

memory location 0Fh, the pointer will be reset to 00h. This cycle of reading consecutive addresses will

continue until the master sends a STOP condition.

Read Sequence

3-wire Serial Interface

The device also support a 3-wire serial interface. The CE pin is used to identify the transmitted data.

The transmission is controlled by the active HIGH signal CE. Each data transfer is a byte, with the LSB

sent first. The first byte transmitted is the Command Byte.

Command Byte

For each data transfer, a Command Byte is initiated to specify which register is accessed. This is to

determine whether a read or write cycle is operational and whether a single byte or burst mode transfer

is to occur.

R/W Signal

The LSB of the Command Byte determines whether the data in the register is to be read or be written

to. If it is

²0² then this means that it is a write cycle. If it is ²1² then this means that it is a read cycle.

Burst Mode

When the Command Byte is 10111110 or 10111111, the device is configured in the burst mode. In this

mode, the address of registers from 00h to 0Fh can be written or read in series, starting with bit 0 of

register address 0.

Rev. 1.40

18

May 27, 2011

HT1382

11 0 10 0 0 1

S

Read

Data(n)

ACK

Data(n+1)

Data(n+x)

P

11 0 10 0 0 0

S

ACK

Slave Address

Write

Register Address(An)

P

ACK

Slave Address

ACK

ACK

ACK

ACK

11 0 10 0 0 0

S

Data(n+1)

Data(n+x)

P

Slave Address

Write

Register Address(An)

Data(n)

ACK

ACK

ACK

ACK

ACK

ACK