I

The HT1382 includes an I

communication between multiple I

(SDA) and the serial clock line (SCL).Both lines are connected to the positive supply via a pull-up

resistor externally.

When the bus is free, both lines will be high. The output stages of the devices connected to the bus

must have open-drain or open-collector output types to implement the wired-AND function necessary

for connection. Data transfer is initiated only when the bus is not busy.

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state

of the data line can only change when the clock signal on the SCL line is LOW.

START and STOP Conditions

A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW

to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START and STOP

conditions are always generated by the master. The bus is considered to be busy after the START

condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays

busy if a repeated START(Sr) is generated instead of a STOP condition. In this respect, a START(S)

and repeated START(Sr) conditions are functionally identical.

Byte Format

Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per

transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with

the most significant bit (MSB) first.

Rev. 1.40

16

May 27, 2011

HT1382

SDA

SCL

Data line stable;

data valid

Change of data

allowed

P

S

SDA

SCL

SDA

SCL

START condition

STOP condition

S

or

Sr

P

or

Sr

SDA

SCL

12

78

9

ACK

12

3-8

9

ACK

P

Sr