HT46R006 datasheet(41/72 Pages) HOLTEK

41 / 72 page

HT48R006/HT46R006

Rev. 1.00

October 24, 2011

Note that the BZ and BZ outputs will both be low if the

PA0 output data bit is cleared to

²0². The condition of

data bit PA1 has no effect on the overall control of the BZ

and BZ pins.

Using this method of frequency generation, and if a

crystal oscillator is used for the system clock, very pre-

cise values of frequency can be generated.

PFD Function -- HT46R006

The Programmable Frequency Divider provides a

means of producing a variable frequency output suitable

for applications, such as piezo-buzzer driving or other

interfaces requiring a precise frequency generator.

The Timer/Event Counter overflow signal is the clock

source for the PFD function, which is controlled by

PFDCS bit in CTRL0. For applicable devices the clock

source can come from either Timer/Event Counter 0 or

Timer/Event Counter 1. The output frequency is con-

trolled by loading the required values into the timer

prescaler and timer registers to give the required division

ratio. The counter will begin to count-up from this preload

generated, causing both the PFD outputs to change

state. The counter will then be automatically reloaded

with the preload register value and continue counting-up.

If the CTRL0 register has selected the PFD function,

then for PFD output to operate, it is essential for the Port

A control register PAC, to setup the PFD pins as outputs.

PA1 must be set high to activate the PFD. The output

data bits can be used as the on/off control bit for the PFD

outputs. Note that the PFD outputs will all be low if the

output data bit is cleared to zero.

Using this method of frequency generation, and if a

crystal oscillator is used for the system clock, very pre-

cise values of frequency can be generated.

I/O Interfacing

The Timer/Event Counter, when configured to run in the

event counter or pulse width measurement mode, re-

quires the use of an external timer pin for its operation.

As this pin is a shared pin it must be configured correctly

to ensure that it is setup for use as a Timer/Event Coun-

ter input pin. This is achieved by ensuring that the mode

select bits in the Timer/Event Counter control register,

select either the event counter or pulse width measure-

ment mode. Additionally the corresponding PAC Port

Control Register bit must be set high to ensure that the

pin is setup as an input. Any pull-high resistor connected

to this pin will remain valid even if the pin is used as a

Timer/Event Counter input.

Programming Considerations

When configured to run in the timer mode, the internal

system clock is used as the timer clock source and is

therefore synchronised with the overall operation of the

microcontroller. In this mode when the appropriate timer

nal interrupt signal directing the program flow to the re-

spective internal interrupt vector. For the pulse width

measurement mode, the internal system clock is also

used as the timer clock source but the timer will only run

when the correct logic condition appears on the external

timer input pin. As this is an external event and not syn-

chronized with the internal timer clock, the

microcontroller will only see this external event when the

next timer clock pulse arrives. As a result, there may be

small differences in measured values requiring pro-

grammers to take this into account during programming.

The same applies if the timer is configured to be in the

event counting mode, which again is an external event

and not synchronized with the internal system or timer

clock.

When the Timer/Event Counter is read, or if data is writ-

ten to the preload register, the clock is inhibited to avoid

errors, however as this may result in a counting error,

this should be taken into account by the programmer.

Care must be taken to ensure that the timers are prop-

erly initialised before using them for the first time. The

associated timer enable bits in the interrupt control reg-

ister must be properly set otherwise the internal interrupt

associated with the timer will remain inactive. The edge

select, timer mode and clock source control bits in timer

control register must also be correctly set to ensure the

timer is properly configured for the required application.

It is also important to ensure that an initial value is first

loaded into the timer registers before the timer is

switched on; this is because after power-on the initial

values of the timer registers are unknown. After the

T i m e r O v e r f l o w

P F D C l o c k

P A 1 D a t a

P F D O u t p u t a t P A 1

PFD Function

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