GS9062-CFE3 datasheet(7/46 Pages) GENNUM

7 / 46 page

GS9062 Data Sheet

22209 - 7

February 2007

7 of 46

SMPTE_BYPASS

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

When set HIGH in conjunction with DVB_ASI = LOW, the device

will be configured to operate in SMPTE mode. All I/O processing

features may be enabled in this mode.

When set LOW, the device will not support the scrambling or

encoding of received SMPTE data. No I/O processing features

will be available.

RSET

Analog

Input

Used to set the serial digital output signal amplitude. Connect to

CD_VDD through 281

Ω +/- 1% for 800mVp-p single-ended output

swing.

CD_VDD

–

Power

Power supply connection for the serial digital cable driver.

Connect to +1.8V DC analog.

SDO_EN/DIS

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to enable or disable the serial digital output stage.

When set LOW, the serial digital output signals SDO and SDO

are disabled and become high impedance.

When set HIGH, the serial digital output signals SDO and SDO

are enabled.

CD_GND

–

Power

Ground connection for the serial digital cable driver. Connect to

analog GND.

23, 24

SDO, SDO

Analog

Output

Serial digital output signal operating at 270Mb/s.

The slew rate of these outputs is automatically controlled to meet

SMPTE 259M specifications.

RESET_TRST

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to reset the internal operating conditions to default settings

and to reset the JTAG test sequence.

Host Mode (JTAG/HOST = LOW)

When asserted LOW, all functional blocks will be set to default

conditions and all input and output signals become high

impedance, including the serial digital outputs SDO and SDO.

Must be set HIGH for normal device operation.

JTAG Test Mode (JTAG/HOST = HIGH)

When asserted LOW, all functional blocks will be set to default

and the JTAG test sequence will be held in reset.

When set HIGH, normal operation of the JTAG test sequence

resumes.

JTAG/HOST

Non

Synchronous

Input

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to select JTAG Test Mode or Host Interface Mode.

When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and

SCLK_TCK are configured for JTAG boundary scan testing.

When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and

SCLK_TCK are configured as GSPI pins for normal host

interface operation.

Table 1-1: Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

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