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LPC1102 датащи(PDF) 12 Page - NXP Semiconductors |
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LPC1102 датащи(HTML) 12 Page - NXP Semiconductors |
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12 / 39 page ![]() LPC1102 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 24 June 2011 12 of 39 NXP Semiconductors LPC1102 32-bit ARM Cortex-M0 microcontroller 7.14.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1102 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.14.1.2 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU or the watchdog timer. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is 40 %. 7.14.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The PLL output frequency must be lower than 100 MHz. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed Fig 4. LPC1102 clock generation block diagram SYSTEM PLL IRC oscillator external clock watchdog oscillator IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) SYSPLLCLKSEL (system PLL clock select) SYSTEM CLOCK DIVIDER AHB clock 0 (system) AHBCLKCTRL[1:18] (AHB clock enable) AHB clocks 1 to 18 (memories and peripherals) SPI0 PERIPHERAL CLOCK DIVIDER SPI0 UART PERIPHERAL CLOCK DIVIDER UART WDT CLOCK DIVIDER WDT WDTUEN (WDT clock update enable) 002aaf527 main clock system clock IRC oscillator 18 |
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