LPC1102 datasheet(4/39 Pages) NXP

4 / 39 page

LPC1102

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Product data sheet

Rev. 4 — 24 June 2011

4 of 39

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

Pinning information

6.1 Pinning

6.2 Pin description

Fig 2.

Pin configuration WLCSP16 package

002aaf525

ball A1

index area

1234

LPC1102UK

Table 3.

LPC1102 pin description table

Symbol

Start

logic

input

Type

Reset

state[1]

Description

RESET/PIO0_0

C1[2]

yes

I; PU

RESET — External reset input with 20 ns glitch filter. A LOW

-going pulse as short as 50 ns on this pin resets the device,

causing I/O ports and peripherals to take on their default states,

and processor execution to begin at address 0.

I/O

PIO0_0 — General purpose digital input/output pin.

PIO0_8/MISO/

CT16B0_MAT0

A2[3]

yes

I/O

I; PU

PIO0_8 — General purpose digital input/output pin.

I/O

MISO0 — Master In Slave Out for SPI.

O-

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI/

CT16B0_MAT1

A3[3]

yes

I/O

I; PU

PIO0_9 — General purpose digital input/output pin.

I/O

MOSI0 — Master Out Slave In for SPI.

O-

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

SWCLK/

PIO0_10/

SCK/CT16B0_MAT2

A4[3]

yes

I; PU

SWCLK — Serial wire clock.

I/O

PIO0_10 — General purpose digital input/output pin.

I/O

SCK — Serial clock for SPI.

O-

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/

AD0/CT32B0_MAT3

B4[4]

yes

I; PU

R — Reserved.

I/O

PIO0_11 — General purpose digital input/output pin.

I-

AD0 — A/D converter, input 0.

I-

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

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