SC1109CSTR datasheet(10/17 Pages) SEMTECH

10 / 17 page

SYNCHRONOUS PWM CONTROLLER WITH

DUAL LOW DROPOUT REGULATOR

CONTROLLERS

PRELIMINARY - October 16, 2000

SC1109

TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com

THEORY OF OPERATION

The SC1109 has integrated a synchronous buck

controller and two Low drop out regulator controllers

into a 16 Pin SOIC package. The switching regulator

provides a 1.2V (VTT) bus termination voltage for use

in AGTL (Assisted Gunning Transceiver Logic), while

the dual LDO regulators provide 1.8V, and 2.5V to

power up the Chipset and the Clock circuitry used in

Pentium

® III Motherboards.

SUPPLIES

Two supplies, VSTBY, and VCC are used to power

the SC1109. VSTBY supply provides the bias for the

Internal Reference, Oscillator, and the LDO FET

controllers. The VCC supply provides the bias for the

Power Good circuitry, and the high side FET Rdson

sensing/over current circuitry, VCC also is used to

drive the low side Mosfet gate. An external 12V

supply or a classical boot strapping technique can

provide the gate drive for the upper Mosfet.

PWM CONTROLLER

SC1109 is a voltage mode buck controller that utilizes

an internally compensated high bandwidth error am-

plifier to sense the VTT output voltage. External

compensation components are not needed and

stable closed loop responce is insured due to the

internal compensation.

START UP SEQUENCE

Initially during the power up, the SC1109 is in under

voltage lock out condition. The latch (SET dominant)

in the hiccup section is set , and the SS/EN pin is

pulled low by the 2uA soft start current source.

Mean while the high side and low side gate drivers

DH, and DL are kept low. Once the VCC exceeds the

UVLO threshold of 4.2V, the latch is reset and the

external soft start capacitor starts to be charged by a

10uA current source.

The gate drives are still kept off until the soft start

capacitors voltage rises above 600mV, when the low

side gate is turned on , and the high side gate is kept

off.

The gate drive status stays the same until the capaci-

tors voltage reaches 1V, when the error amplifier

output starts to cross the oscillator triangular ramp of

1V to 2V.

As the SS/EN pin continues to rise, the error amplifier

output also rises at the same rate and the duty cycle

increases.

Once the VTT output has reached regulation and is

within 1.2V

± 12% , an open collector power good flag

is activated, and the error amplifier output will no

longer be clamped to the SS/EN voltage and will stay

between 1V to 2V and maintain regulation of

± 1%.

The SS/EN voltage continues to rise up to 2.5V and

will stay at that voltage level during normal operation.

If an over current condition occurs, the SS/EN pin will

discharge by a 2uA current source, from 2.5V to

800mV. During this time both DH, and DL will be

turned off. Once the SS/EN reaches 800mV, the low

side gate will be turned on, and the SS/EN pin will

again start to be charged by the 10uA current source,

and the same soft start sequence mentioned above

will be repeated.

Vcc

PowerGood

Softstart

PhaseNode

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