Soft-start

L6738

14/32

Doc ID 18133 Rev 1

5

Soft-start

The L6738 implements a soft-start to smoothly charge the output filter avoiding high in-rush

currents to be required to the input power supply. During this phase, the device increases

the internal reference from zero up to 0.8 V in closed loop regulation. The soft-start is

implemented only when VCC and VCCDR are above their own UVLO threshold and the EN

pin is set free.

When SS takes place, the IC initially waits for 1024 clock cycles and then starts ramping-up

the reference in 1024 clock cycles in closed-loop regulation. At the end of the digital soft-

start, the PWRGOOD signal is set free with 3x clock cycles delay.

Protections are active during this phase as follows:

●

undervoltage is enabled when the reference voltage reaches 80 % of the final value

●

overvoltage is always enabled

●

FB disconnection is enabled

Soft-start time depends on the programmed frequency, initial delay and reference ramp-up

lasts for 1024 clock cycles. SS time and initial delay can be determined as follows:

5.1

LS-less startup

In order to avoid any kind of negative undershoot on the load side during startup, the L6738

performs a special sequence in enabling the drivers for both sections: during the soft-start

phase, the LS MOSFET is kept OFF until the first PWM pulse. This particular sequence

avoids the dangerous negative spike on the output voltage that can happen if starting over a

pre-biased output.

Low-side MOSFET turn-on is masked only from the control loop point of view: protections

are still allowed to turn on the low-side MOSFET in the case of overvoltage, if needed.

Figure 5.

LS-less startup (left) vs. non-LS-less startup (right)

T

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1024

Fsw kHz

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