Application details

L6728D

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Doc ID 16498 Rev 1

b)

c)

d)

e)

Check that the compensation network gain is lower than open loop EA gain before

f)

Check the phase margin obtained (it should be greater than 45°) and repeat if

necessary.

10.2

Layout guidelines

The L6728D provides control functions and high current integrated drivers to implement

high-current step-down DC-DC converters. In this type of application, a good layout is very

important.

The first priority when placing components for these applications must be reserved for the

power section, minimizing the length of each connection and loop as much as possible. To

minimize noise and voltage spikes (EMI and losses) power connections (highlighted in

Figure 7) must be a part of a power plane and in any case constructed with wide and thick

copper traces. The loop must be minimized. The critical components, i.e. the power

MOSFETs, must be close to each other. The use of multi-layer printed circuit boards is

recommended.

placed close to the power section in order to eliminate the stray inductance generated by the

copper traces. Low ESR and ESL capacitors are preferred. MLCC are suggested to be

connected near the HS drain.

Use the appropriate number of VIAs when power traces have to move between different

planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover,

reproducing the same high-current trace on more than one PCB layer reduces the parasitic

resistance associated with that connection.

inductance and resistance associated with the copper trace, and also adding extra

decoupling capacitors along the way to the load when this results in being far from the bulk

capacitor bank.

C

F

1

π R

F

F

LC

⋅⋅

-----------------------------

=

C

P

C

F

2

π R

F

C

F

F

ESR

1

–

⋅⋅

⋅

----------------------------------------------------------

=

R

S

R

FB

F

SW

2F

⋅

LC

------------------

1

–

---------------------------

=

C

S

1

π R

S

F

SW

⋅⋅

-------------------------------

=