Application details

L6728D

16/33

Doc ID 16498 Rev 1

10

Application details

10.1

Compensation network

The control loop shown in Figure 5 is a voltage mode control loop. The output voltage is

regulated to the internal reference (when present, the offset resistor between the FB node

and GND can be neglected in control loop calculation).

The error amplifier output is compared to the oscillator sawtooth waveform to provide the

PWM signal to the driver section. The PWM signal is then transferred to the switching node

The converter transfer function is the small signal transfer function between the output of the

ΔV

Figure 5.

PWM control loop

function ideally equal to -Z

The compensation goal is to close the control loop while assuring high DC regulation

accuracy, good dynamic performance and stability. To achieve this, the overall loop needs

high DC gain, high bandwidth and good phase margin.

High DC gain is achieved by giving an integrator shape to the compensation network

the control loop gain must cross the 0 dB axis with -20 dB/decade slope.

As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.

L

R

C

OUT

ESR

R

F

C

F

C

P

R

FB

C

S

OSC

V

IN

ΔV

OSC

+

+

_

_

V

OUT

V

REF

Z

FB

PWM

COMPARATOR

ERROR

AMPLIFIER

R

S