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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L6726ATR датащи(PDF) 14 Page - STMicroelectronics |
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L6726ATR датащи(HTML) 14 Page - STMicroelectronics |
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14 / 35 page  Protections L6726A 14/35 Doc ID 12754 Rev 4 Figure 6. OC threshold setting procedure timings (top) and waveforms (bottom) 7.3 Undervoltage lock out In order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, UVLO is provided: the device will start up when VCC reaches UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold. The 4.1 V maximum UVLO upper threshold allows L6726A to be supplied from 5 V and 12 V busses in or-ing diode configuration. Figure 7. OCP trip, default threshold, LS: STD38NH02L (left) UVLO turn off (right) VCC Enable Th COMP 700mV LGATE PWM ramp bottom edge UVLO Th R OCSET not connected Setting Procedure VCC Enable Th COMP 700mV LGATE PWM ramp bottom edge UVLO Th 5.5ms - 6.5ms R OCSET connected Setting Procedure t DELAY t DELAY |
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