PCF85176T datasheet(14/43 Pages) NXP

14 / 43 page

PCF85176_1

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Product data sheet

Rev. 01 — 14 April 2010

14 of 43

NXP Semiconductors

PCF85176

Universal LCD driver for low multiplex rates

7.5 Oscillator

7.5.1 Internal clock

The internal logic of the PCF85176 and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCF85176 in the system that are connected in cascade.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD

frame signal frequency is determined by the clock frequency (fclk).

A clock signal must always be supplied to the device; removing the clock may freeze the

LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The PCF85176 timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCF85176 in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame signal whose frequency is derived from the clock frequency. The frame signal

frequency is a fixed division of the clock frequency from either the internal or an external

clock:

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.8 Segment outputs

The LCD drive section includes 40 segment outputs S0 to S39 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display register. When

less than 40 segment outputs are required, the unused segment outputs should be left

open-circuit.

7.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals

and may also be paired to increase the drive capabilities.

clk

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