PCF85176T datasheet(32/43 Pages) NXP

32 / 43 page

PCF85176_1

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Product data sheet

Rev. 01 — 14 April 2010

32 of 43

NXP Semiconductors

PCF85176

Universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF85176. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments or by defining a multiplex drive mode when PCF85176

with different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCF85176 asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCF85176 to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF85176 are shown in Figure 24.

The contact resistance between the SYNC on each cascaded device must be controlled.

If the resistance is too high, the device is not able to synchronize properly; this is

particularly applicable to chip-on-glass applications. The maximum SYNC contact

resistance allowed for the number of devices in cascade is given in Table 19.

(1) Is master (OSC connected to VSS).

(2) Is slave (OSC connected to VDD).

Fig 23. Cascaded PCF85176 configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC

40 segment drives

4 backplanes

40 segment drives

LCD PANEL

PCF85176

SA0

VSS

VDD

VLCD

VDD

VLCD

013aaa297

SDA

SCL

SYNC

CLK

OSC

BP0 to BP3

(open-circuit)

SA0

PCF85176

BP0 to BP3

2Cb

≤

(1)

(2)

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