PCF85176 datasheet(33/43 Pages) NXP

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PCF85176_1

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Product data sheet

Rev. 01 — 14 April 2010

33 of 43

NXP Semiconductors

PCF85176

Universal LCD driver for low multiplex rates

The PCF85176 can always be cascaded with other devices of the same type or

conditionally with other devices of the same family. This allows optimal drive selection for

a given number of pixels to display. Figure 21 and Figure 24 show the timing of the

synchronization signals.

In a cascaded configuration only one PCF85176 master must be used as clock source. All

other PCF85176 in the cascade must be configured as slave such that they receive the

clock from the master.

If an external clock source is used, all PCF85176 in the cascade must be configured such

as to receive the clock from that external source (pin OSC connected to VDD). Thereby it

must be ensured that the clock tree is designed such that on all PCF85176 the clock

propagation delay from the clock source to all PCF85176 in the cascade is as equal as

possible since otherwise synchronization artefacts may occur.

In mixed cascading configurations, care has to be taken that the specifications of the

individual cascaded devices are met at all times.

Table 19.

SYNC contact resistance

Number of devices

Maximum contact resistance

26 k

3 to 5

2.2 k

6 to 10

1.2 k

10 to 16

700

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