PCF8593

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Product data sheet

Rev. 04 — 6 October 2010

11 of 35

NXP Semiconductors

PCF8593

Low power clock and calendar

7.8 Event counter mode

Event counter mode is selected by bits 4 and 5 which are logic 10 in the control and status

register. The event counter mode is used to count pulses externally applied to the

oscillator input (OSCO left open-circuit).

The event counter stores up to 6 digits of data, which are stored as 6 hexadecimal values

located in the registers 1h, 2h, and 3h. Therefore, up to 1 million events may be recorded.

An event counter alarm occurs when the event counter registers match the value

programmed in the registers 9h, Ah, and Bh, and the event alarm is enabled (bits 4 and 5

which are logic 01 in the alarm control register). In this event, the alarm flag (bit 1 of the

control and status register) is set. The inverted value of this flag can be transferred to the

interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. In

(1) If the alarm enable bit of the control and status register is reset (logic 0), a 1 Hz signal is observed on the interrupt pin INT.

Fig 11. Alarm and timer interrupt logic diagram

INT

7

654

321

0

76

5

4

3

2

10

timer overflow

interrupt

alarm

interrupt

TIMER

ALARM

CLOCK/CALENDAR

MUX

timer

control

timer

alarm

overflow

alarm

control

clock

alarm

counter

control

mode

select

oscillator

CONTROL/STATUS

ALARM CONTROL

REGISTER

013aaa377