PCA9505 datasheet(8/34 Pages) NXP

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PCA9505_9506

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Product data sheet

Rev. 4 — 3 August 2010

8 of 34

NXP Semiconductors

PCA9505/06

40-bit I2C-bus I/O port with RESET, OE and INT

The lowest 6 bits are used as a pointer to determine which register will be accessed. The

registers are:

• IP: Input Port registers (5 registers)

• OP: Output Port registers (5 registers)

• PI: Polarity Inversion registers (5 registers)

• IOC: I/O Configuration registers (5 registers)

• MSK: Mask interrupt registers (5 registers)

If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically

incremented after a read or write. This allows the user to program and/or read the

5 register banks sequentially.

If more than 5 bytes of data are written and AI = 1, previous data in the selected registers

will be overwritten. Reserved registers are skipped and not accessed (refer to Table 3).

If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not

incremented after data is read or written. During a read operation, the same register bank

is read each time. During a write operation, data is written to the same register bank each

time.

Only a Command register code with the 5 least significant bits equal to the 25 allowable

values as defined in Table 3 are valid. Reserved or undefined command codes must not

be accessed for proper device functionality. At power-up, this register defaults to 0x80,

with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.

During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and

IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since

these are read-only registers.

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