PCA9505 datasheet(2/34 Pages) NXP

2 / 34 page

PCA9505_9506

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 3 August 2010

2 of 34

NXP Semiconductors

PCA9505/06

40-bit I2C-bus I/O port with RESET, OE and INT

Inputs:

Programmable Interrupt Mask Control for input pins that do not require an interrupt

when their states change

Polarity Inversion register allows inversion of the polarity of the I/O pins when read

Active LOW reset (RESET) input pin resets device to power-up default state

3 programmable address pins allowing 8 devices on the same bus

Designed for live insertion

Minimize line disturbance (IOFF and power-up 3-state)

Signal transient rejection (50 ns noise filter and robust I2C-bus state machine)

Low standby current

−40 °Cto+85 °C operation

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA

Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages

Applications

Servers

RAID systems

Industrial control

Medical equipment

PLCs

Cell phones

Gaming machines

Instrumentation and test measurement

Ordering information

Table 1.

Ordering information

Type number

Topside mark

Package

Name

Description

Version

PCA9505DGG

TSSOP56

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

PCA9506DGG

TSSOP56

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

PCA9506BS

HVQFN56

plastic thermal enhanced very thin quad flat package;

no leads; 56 terminals; body 8

× 8 × 0.85 mm

SOT684-1

PCA9505 датащи(PDF) 2 Page - NXP Semiconductors

PCA9505 датащи(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL