MAX16929BGUI datasheet(22/25 Pages) MAXIM

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�� Maxim Integrated Products 22

MAX16929

Automotive TFT-LCD Power Supply with Boost

Converter and Gate Voltage Regulators

Boost Converter

Power dissipation in the boost converter is primarily due

to conduction and switching losses in the low-side FET.

Conduction loss is produced by the inductor current

flowing through the on-resistance of the FET during the

on-time. Switching loss occurs during switching transi-

tions and is a result of the finite time needed to fully turn

on and off the FET. Power dissipation in the boost con-

verter can be estimated with the following formula:

PLXP ≈ [(IIN(DC,MAX) × √D)2 × RDS_ON(LXP)] + VSH ×

IIN(DC,MAX) × fSW × [(tR-V + tF-I) + (tR-I + tF-V)]

where IIN(DC,MAX) is the maximum expected average

input (i.e., inductor) current, D is the duty cycle of the

boost converter, RDS_ON(LXP) is the on-resistance of

the internal low-side FET, VSH is the output voltage, and

fSW is the switching frequency of the boost converter.

RDS_ON(LXP) is 110mI (typ) and fSW is 2.2MHz.

The voltage and current rise and fall times at the LXP

node are equal to tR-V (voltage rise time), tF-V (voltage fall

time), tR-I (current rise time), and tF-I (current fall time),

and are determined as follows:

SCHOTTKY

R-V

SCHOTTKY

F-V

IN(DC,MAX)

R-I

IN(DC,MAX)

F-I

KR-V, KF-V, KR-I, and KF-I are the voltage and current

slew rates of the LXP node and are supply dependent.

Use Table 5 to determine their values.

Positive-Gate Voltage Regulator

Use the lowest number of charge-pump stages possible

in supplying power to the positive-gate voltage regulator.

Doing so minimizes the drain-source voltage of the inte-

grated pMOS switch and power dissipation. The power

dissipated in the switch is given as:

PGH = (VCP - VGH) × ILOAD(MAX)_GH

Ensure that the voltage on CP does not exceed the

CP overvoltage threshold as given in the Electrical

Characteristics table.

Negative-Gate Voltage Regulator

Use the lowest number of charge-pump stages possible

to provide the negative voltage to the negative-gate

voltage regulator. Estimate the power dissipated in the

negative-gate voltage regulator using the following:

PGL = (VINA + |VCN| - VBE) × IDRVN

where VBE is the base-emitter voltage of the external npn

bipolar transistor, and IDRVN is the current sourced from

DRVN to the RBE bias resistor and to the base of the

transistor, which is given by:

DRVN

h +1

1.8V/3.3V Regulator Controller

The power dissipated in the 1.8V/3.3V regulator controller

is given by:

PREG = (VINA - VOUT_REG - VBE) × IDR

where VOUT_REG = 1.8V or 3.3V, VBE is the base-emitter

voltage of the external npn bipolar transistor, and IDR is

the current sourced from DR to the base of the transistor.

IDR is given by:

LOAD

where ILOAD is load current of the 1.8V/3.3V regulator

controller, and hFE is the current gain of the transistor.

Table 5. LXP Voltage and Current Slew Rates vs. Supply Voltage

VINA (V)

LXP VOLTAGE AND CURRENT SLEW RATES

RISING VOLTAGE

SLEW RATE

KR-V (V/ns)

FALLING VOLTAGE

SLEW RATE

KF-V (V/ns)

RISING CURRENT

SLEW RATE

KR-I (A/ns)

FALLING CURRENT

SLEW RATE

KF-I (A/ns)

3.3

0.52

1.7

0.13

0.38

1.35

0.3

0.44

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