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MAX16929

Automotive TFT-LCD Power Supply with Boost

Converter and Gate Voltage Regulators

Pin Description (continued)

PIN

NAME

FUNCTION

10

FBB

Buck Converter Feedback Input. FBB is regulated to either 3.3V or 5V. Connect FBB to the output-volt-

age node, OUTB, as shown in the Typical Application Circuit.

11

AVL

Buck Converter Internal 5V Regulator. Connect a 1FF capacitor between AVL and the analog ground

plane. Do not use AVL to power external circuitry.

12

BST

Buck Converter Bootstrap Capacitor Connection. Connect a 0.1FF capacitor between BST and LXB.

13, 14

LXB

Buck Converter Inductor Connection. Connect the inductor, boost capacitor, and catch diode at this

node.

15, 16

INB

Buck Converter Power Input. Connect to a 4V to 28V supply. Connect a 1FF or larger ceramic capaci-

tor in parallel with a 47FF bulk capacitor from INB to the power ground plane. Connect both INB power

inputs together.

17

ENB

Buck Converter Enable Input. ENB is a high-voltage compatible input. Connect to INB for normal opera-

tion and connect to ground to disable the buck converter.

18, 23

GND

Analog Ground

19

PGOOD

Open-Drain Power-Good Output. Connect PGOOD to INA through an external pullup resistor.

20

CP

Positive-Gate Voltage Regulator Power Input. Connect CP to the positive output of the external charge

Characteristics table.

21

GH

Positive-Gate Voltage Regulator Output

22

DRVN

Negative-Gate Voltage Regulator Driver Output. DRVN is the open drain of an internal p-channel FET.

Connect DRVN to the base of an external npn pass transistor.

24

COMPI

Boost Slope Compensation Connection. Connect a capacitor between COMPI and GND to set the

slope compensation.

25

FBGH

Positive-Gate Voltage Regulator Feedback Input. FBGH is regulated to 1V. Connect FBGH to the center

of a resistive divider connected between GH and GND.

26

FBGL

Negative-Gate Voltage Regulator Feedback Input. FBGL is regulated to 0.25V. Connect FBGL to the

center of a resistive divider connected between REF and the output of the negative-gate voltage

regulator.

27

REF

1.25V Reference Output. Bypass REF to GND with a 0.1FF ceramic capacitor.

28

SEQ

Sequencing Input. SEQ has an internal 500kI pulldown resistor. SEQ determines the sequence in

—

EP

Exposed Pad. Connect to a large contiguous copper ground plane for optimal heat dissipation. Do not

use EP as the only electrical ground connection.