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ACS411CS датащи(PDF) 38 Page - Semtech Corporation

номер детали ACS411CS
подробное описание детали  Acapella Optical Modem IC
PDF  43 Pages
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производитель  SEMTECH [Semtech Corporation]
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ACS411CS датащи(HTML) 38 Page - Semtech Corporation

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38
ACS411CS PRE-RELEASE Issue 6.0 July 1999.
Pin Description ACS4110 part 3.
Pin Description ACS4110 part 4.
Pin description ACS4110 part 5 - uP interface.
Pin
Sym
IO
Name
Description
40
32
26
20
14
8
176
170
164
46
54
60
66
72
78
83
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
TCLK8
TCLK9
TCLK10
TCLK11
TCLK12
TCLK13
TCLK14
TCLK15
TCLK16
I/O
Transmit
clocks
Transmit Clock 1-16, samples
TPOS/TNEG data on clock
edge selected by input TRSEL.
35
29
23
17
11
3
173
167
157
43
49
57
63
69
75
86
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
O
Receive clocks
Receive Clock, RPOS/RNEG
data is valid on edge selected
by input RESEL.
113
112
111
CM1
CM2
CM3
I
Configuration
Modes
CM(3:1) select the
Configuration Modes such as
full duplex, master and slave
mode.
90
ERRL
O
Error Latch
If errors are detected in the
8B10B coding rules ERRL will
be forced high.. ERRL will be
reset low if the device is forced
out of synchronisation e.g.
PORB = 0.
89
ERRC
O
Error count
ERRC will go high coincident
with each error detected in the
8B10B coding rules. Errors may
be accumulated by means of an
external electronic counter.
119
118
117
DR1
DR2
DR3
I
Data Rate
Select
The DR(3:1) input select the
Data Rates and number of
channels. See section headed
Data Rate Selection.
103
CKC
I
Clock Select
When CKC = 0, TCLK1-16
are configured as an output.
When CKC = 1, TCLK1-16
are configured as an input.
102
CKM
I
Clock Select
When CKM = 0, TmCLK is
configured as an output.
When CKM = 1, TmCLK is
configured as an input
97
CONTX
I
Continuous
transmit
114
IREF
I
Current
reference
A 51K
Ω 1% resistor should be
placed between IREF and
GND.
Pin
Sym
IO
Name
Description
127
126
125
UPSEL1
UPSEL2
UPSEL3
I
uP Interface
uP interface mode control.
133
ALE
I
uP Interface
uP bus address latch enable.
1) POL3 in pin control mode
UPSEL(3:1) = 0.
134
RDB
I
uP Interface
uP bus read (active low).
2) POL2 in pin control mode
UPSEL(3:1) = 0.
135
WRB
I
uP Interface
uP bus write (active low).
3) POL1 in pin control mode
UPSEL(3:1) = 0.
136
CSB
IO
uP Interface
uP bus chip select (active low).
4) CKLOCAL in pin control
modeUPSEL(3:1) = 0.
137
RDY
O
uP Interface
uP bus ready/data
acknowledge.
140
141
142
143
144
A0
A1
A2
A3
A4
IO
uP Interface
uP bus address.
145
146
147
148
149
150
151
152
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
IO
uP Interface
uP bus address/data.
Pin
Sym
IO
Name
Description
91
LOSS
O
LOSS of
Signal
When LOSS = 1, receive data
is unreliable.
When LOSS = 0, receive data
is reliable.
96
TmD1
I
Transmit
maintenance
Data
NRZ maintenance channel.
TmD is sampled on the
TmCLK clock edge defined by
TRSEL.
93
RmD2
O
Receive
maintenance
Data
NRZ maintenance channel.
RmD is sampled on the
RmCLK clock edge defined by
RESEL.
101
100
99
MSEL1
MSEL2
MSEL3
I
Maintenance
channel data
rate selection
The MSEL(3:1) input select the
Data Rates of channels. See
section headed Maintenance
Data Rate Selection.
98
ENRSB
I
Enable
Remote Setup
Remote device setup.



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