ACS411CS datasheet(12/43 Pages) SEMTECH

12 / 43 page

ACS411CS PRE-RELEASE Issue 6.0 July 1999.

Microprocessor Interface

Bus Interface Mode Selection

The ACS4110 incorporates an 8-bit parallel

microprocessor bus interface, which can be configured

for the following modes via the bus interface mode

control pins UPSEL(3:1) as defined in Table 9.

UPSEL(3:1) Mode

Description

111 (7)

OFF

Interface disabled

110 (6)

OFF

Interface disabled

101 (5)

SERIAL

Serial uP bus interface

100 (4)

MOTOROLA

Motorola interface

011 (3)

INTEL

Intel compatible bus interface

010 (2)

MULTIPLEXED Multiplexed bus interface

001 (1)

EPROM

EPROM read mode

000 (0)

OFF

Interface disabled

Table 9: Microprocessor Interface Mode Selection

Note: Bit 0 is the least significant bit for all modes used

here, and the byte structure complies to little endian

format (byte 0 is least significant and stored at lowest

address).

In OFF Mode, the bus interface is disabled. Control of

the device is solely via I/O pins. This will result in limited

programmability, as for example individual set-ups for

remote loop-back and local loop-back for each channel

are not possible, only a collective one. In this mode, all

BUS I/O pins are tri-stated or used as additional input

pins (ie. POL(3:1), CKLOCAL).

EPROM mode

The EPROM mode (UPSEL = 1) enables the device to

read its set-up from a memory device. An internal state

machine controls the access to the memory. All

addresses in the memory map are read, and the device

is set up according to the corresponding data. The

access time is scaled to interface with the

AMD

AM27C020 at lowest speed (250ns) specification.

The valid read addresse 0, 0xAA is used to check if a

memory device is actually attached to the device. If no

memory is attached, the bus interface reverts to the

default OFF mode. All other read addresses are not

valid. The bus interface pins used in EPROM mode are

defined in Table 10.

Dir

Description

CSB

Active low chip select/output enable

A(4:0)

Address output to EPROM

AD(7:0)

Data input from EPROM

Table 10: uP Bus Interface Pins for EPROM mode.

MULTIPLEXED mode

The MULTIPLEXED mode (UPSEL = 2) enables the

ACS4110 to interface with a microprocessor using a

combined multiplexed address/data bus. The bus

interface pins are defined in Table 11.

Dir

Description

CSB

Active low chip select

ALE

Address latch enable

RDB

Active low read enable

WRB

Active low write enable

AD(7:0)

Address / Data bus

RDY

Ready

Table 11: uP Bus Interface Pins for MULTIPLEXED mode.

INTEL mode

The INTEL mode (UPSEL = 3) enables the ACS4110

to interface with a Intel 80x86 type microprocessor

bus. The bus interface pins used are defined in Table

12.

Dir

Description

CSB

Active low chip select

RDB

Active low read enable

WRB

Active low write enable

A(4:0)

Address bus

AD(7:0)

Data bus

RDY

Ready

Table 12: uP Bus Interface Pins for INTEL mode.

MOTOROLA mode

The MOTOROLA mode (UPSEL = 4) enables the

ACS4110 to interface with a Motorola 680x0 type

microprocessor bus. The bus interface pins used are

defined in Table 13.

Dir

Description

CSB

Active low chip select

WRB

Read / write bar select

A(4:0)

Address bus

AD(7:0)

Data bus

RDY

Active low data transfer

acknowledge (DTACK)

Table 13: uP Bus Interface Pins for MOTOROLA mode.

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