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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD6649EBZ датащи(PDF) 9 Page - Analog Devices |
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AD6649EBZ датащи(HTML) 9 Page - Analog Devices |
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9 / 40 page  AD6649 Rev. 0 | Page 9 of 40 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to the rising edge of CLK setup time 0.3 ns tHSYNC SYNC to the rising edge of CLK hold time 0.4 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns Timing Diagrams CLK+ CLK– DCO+ DCO– CHA3 CHB3 CHA4 CHB4 CHA5 D0+ TO D13+ D0– TO D13– tCH tCLK tDCO tPD tSKEW CHA1 CHB1 CHA0 CHB0 CHA2 CHB2 CHB5 CHA6 CHB6 Figure 2. Interleaved LVDS Mode Data Output Timing tSSYNC tHSYNC SYNC CLK+ Figure 3. SYNC Timing Inputs |
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