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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MM912G634CV2AP датащи(PDF) 73 Page - Freescale Semiconductor, Inc |
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MM912G634CV2AP датащи(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 345 page  Wake-up / Cyclic Sense MM912_634 Advance Information, Rev. 4.0 Freescale Semiconductor 73 4.9.2.2 Timing Control Register (TCR) 3 - L3WE Wake-up Input 3 Enabled - L3 Wake-up Select Bit. 0 - L3Wake-up Disabled 1 - L3 Wake-up Enabled 2- L2WE Wake-up Input 2 Enabled - L2 Wake-up Select Bit. 0 - L2 Wake-up Disabled 1 - L2 Wake-up Enabled 1 - L1WE Wake-up Input 1 Enabled - L1 Wake-up Select Bit. 0 - L1 Wake-up Disabled 1 - L1 Wake-up Enabled 0 - L0WE Wake-up Input 0 Enabled - L0 Wake-up Select Bit. 0 - L0 Wake-up Disabled 1 - L0 Wake-up Enabled Table 96. Timing Control Register (TCR) Offset(70) 0x13 Access: User read/write 7 654 32 10 R FWM CST W Reset 0 000 00 00 Note: 70. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 95. WCR - Register Field Descriptions Field Description |
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