IMX28CEC datasheet(6/70 Pages) FREESCALE

6 / 70 page

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

Table 4 describes the digital and analog modules of the device.

Application UART (AUART): Interfaces supported

4 dedicated / 5 with muxing

Synchronous Serial Port (SSP): Supported through dedicated pins

3 dedicated / 4 with muxing

I2C

1 dedicated / 2 with muxing

SPDIF

SAIF

FlexCAN

LCD interface

24 bits

High-speed ADC

Yes

LRADC (touchscreen, keypad...)

Yes

Ethernet MAC and switch

2 MACs with switch

Universal Serial Bus (USB)

Table 4. i.MX28 Digital and Analog Modules

Block

Mnemonic

Block Name

Subsystem

Brief Description

APBHDMA

AHB to APBH

Bridge with

DMA

System control

The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for

memory-mapped I/O to the APB devices, as well a central DMA facility for

devices on this bus. The bridge provides a peripheral attachment bus running

on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous

to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.)

The DMA controller transfers read and write data to and from each peripheral

on APBH bridge.

APBXDMA

AHB to APBX

Bridge with

DMA

System control

The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for

memory-mapped I/O to the APB devices, as well a central DMA facility for

devices on this bus. The AHB-to-APBX bridge provides a peripheral

attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that

the APBX runs on a crystal-derived clock, as compared to APBH, which is

synchronous to HCLK.) The DMA controller transfers read and write data to

and from each peripheral on APBX bridge.

ARM9 or

ARM926

ARM926EJ-S

CPU

ARM®

The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM

real-time debug modules. It contains the 16-Kbyte L1 instruction cache,

32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.

AUART(5)

Application

UART

interface

Connectivity

peripherals

Each of the UART modules supports the following serial data

transmit/receive protocols and configurations:

• 7- or 8-bit data words, one or two stop bits, programmable parity (even,

odd, or none)

• Programmable baud rates up to 3.25 MHz. This is a higher maximum

baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard

and previous Freescale UART modules. 16-byte FIFO on Tx and 16-byte

FIFO on Rx supporting auto-baud detection

Table 3. i.MX28 Functions (continued)

Function

BGA289

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