MC68340 datasheet(13/962 Pages) MOTOROLA

13 / 962 page

Table of Contents

Paragraph

Title

Page

Number

MOTOROLA

MC68360 USER’S MANUAL

6.9.3.7

Periodic Interrupt Timer Register (PITR)............................................... 6-38

6.9.3.8

Software Service Register (SWSR)....................................................... 6-39

6.9.3.9

CLKO Control Register (CLKOCR) ....................................................... 6-39

6.9.3.10

PLL Control Register (PLLCR) .............................................................. 6-40

6.9.3.11

Clock Divider Control Register (CDVCR) .............................................. 6-42

6.9.3.12

Breakpoint Address Register (BKAR) ................................................... 6-44

6.9.3.13

Breakpoint Control Register (BKCR)..................................................... 6-44

6.9.4

Port E Pin Assignment Register (PEPAR) ............................................ 6-48

6.10

Memory Controller................................................................................. 6-50

6.10.1

Memory Controller Key Features .......................................................... 6-50

6.10.2

Memory Controller Overview................................................................. 6-51

6.11

General-Purpose Chip-Select Overview (SRAM Banks)....................... 6-56

6.11.1

Associated Registers............................................................................. 6-56

6.11.2

8-, 16-, and 32-Bit Port Size Configuration............................................ 6-56

6.11.3

Write Protect Configuration ................................................................... 6-56

6.11.4

Programmable Wait State Configuration............................................... 6-56

6.11.5

Address and Address Space Checking................................................. 6-57

6.11.6

SRAM Bank Parity................................................................................. 6-57

6.11.7

External Master Support........................................................................ 6-57

6.11.8

Global (Boot) Chip-Select Operation..................................................... 6-58

6.11.9

SRAM Bus Error.................................................................................... 6-58

6.12

DRAM Controller Overview (DRAM Banks) .......................................... 6-58

6.12.1

DRAM Normal Access Support ............................................................. 6-60

6.12.2

DRAM Page Mode Support................................................................... 6-60

6.12.3

DRAM Burst Access Support ................................................................ 6-61

6.12.4

DRAM Bank Parity ................................................................................ 6-62

6.12.5

Refresh Operation ................................................................................. 6-62

6.12.6

DRAM Bank External Master Support................................................... 6-63

6.12.7

Double-Drive RAS Lines ....................................................................... 6-63

6.12.8

DRAM Bus Error.................................................................................... 6-63

6.13

Programming Model .............................................................................. 6-64

6.13.1

Global Memory Register (GMR)............................................................ 6-64

6.13.2

Memory Controller Status Register (MSTAT)........................................ 6-69

6.13.3

Base Register (BR) ............................................................................... 6-70

6.13.4

Option Register (OR)............................................................................. 6-74

6.13.5

DRAM-SRAM Performance Summary; ................................................. 6-78

Section 7

Communication Processor Module (CPM)

Introduction.............................................................................................. 7-1

7.1

RISC Controller ....................................................................................... 7-3

7.1.1

RISC Controller Configuration Register (RCCR).................................... 7-4

7.1.2

RISC Microcode Revision Number......................................................... 7-5

7.2

Command Set ........................................................................................ 7-5

7.2.1

Command Register Examples................................................................. 7-8

7.2.2

Command Execution Latency ................................................................. 7-8

MC68340 датащи(PDF) 13 Page - Motorola, Inc

MC68340 датащи(HTML) 13 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL