70592C datasheet(175/314 Pages) MICROCHIP

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DS70592C-page 175

PIC24HJXXXGPX06A/X08A/X10A

18.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules avail-

able in the PIC24HJXXXGPX06A/X08A/X10A device

family. The UART is a full-duplex asynchronous system

that can communicate with peripheral devices, such as

personal computers, LIN, RS-232 and RS-485 inter-

faces. The module also supports a hardware flow con-

trol option with the UxCTS and UxRTS pins and also

includes an IrDA® encoder and decoder.

The primary features of the UART module are:

• Full-Duplex, 8 or 9-bit Data Transmission through

the UxTX and UxRX pins

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS pins

• Fully Integrated Baud Rate Generator with 16-bit

Prescaler

• Baud rates ranging from 10 Mbps to 38 bps at 40

MIPS

• 4-deep First-In-First-Out (FIFO) Transmit Data

Buffer

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

• A Separate Interrupt for all UART Error Conditions

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

•IrDA® Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA® Support

A simplified block diagram of the UART is shown in

Figure 18-1. The UART module consists of the key

important hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 18-1:

UART SIMPLIFIED BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the PIC24HJXXXGPX06A/X08A/X10A

family of devices. However, it is not

intended to be a comprehensive refer-

ence source. To complement the infor-

mation in this data sheet, refer to Section

17.

“UART”

(DS70232)

the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as

a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as

a result of a UART1 or UART2 transmission or reception.

2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word

(i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).

UxRX

Hardware Flow Control

UART Receiver

UART Transmitter

UxTX

/BCLK

Baud Rate Generator

UxRTS

IrDA®

UxCTS

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