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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8309EC датащи(PDF) 17 Page - Freescale Semiconductor, Inc |
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MPC8309EC датащи(HTML) 17 Page - Freescale Semiconductor, Inc |
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17 / 82 page  MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 17 DDR2 SDRAM Figure 4 shows the input timing diagram for the DDR controller. Figure 4. DDR Input Timing Diagram 6.2.2 DDR2 SDRAM Output AC Timing Specifications Table 16 provides the output AC timing specifications for the DDR2 SDRAM interfaces. Table 16. DDR2 SDRAM Output AC Timing Specifications At recommended operating conditions with GVDD of 1.8V ± 100mV. Parameter Symbol1 Min Max Unit Notes MCK cycle time, (MCK/MCK crossing) tMCK 5.988 8 ns 2 ADDR/CMD output setup with respect to MCK tDDKHAS ns 3 333 MHz 266 MHz 2.4 2.5 — ADDR/CMD output hold with respect to MCK tDDKHAX ns 3 333 MHz 266 MHz 2.4 2.5 — MCS output setup with respect to MCK tDDKHCS ns 3 333 MHz 266 MHz 2.4 2.5 — MCS output hold with respect to MCK tDDKHCX ns 3 333 MHz 266 MHz 2.4 2.5 — MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4 MCK[n] MCK[n] tMCK MDQ[x] MDQS[n] tDISKEW D1 D0 tDISKEW |
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