PIC12F752 datasheet(87/204 Pages) MICROCHIP

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Preliminary

DS41576A-page 87

PIC12F752/HV752

11.6

Blanking Control

Input blanking is a function whereby the event inputs

can be masked or blanked for a short period of time.

This is to prevent electrical transients caused by the

turn-on/off of power components from generating a

false input event.

The COG contains two 4-bit blanking counters. The

counters are cross coupled with the events they are

blanking. The falling edge blanking counter is used to

blank rising edge input events and the rising edge

blanking counter is used to blank falling edge input

events. Once started, blanking extends for the time

specified by the corresponding blanking counter.

Blanking is timed by counting COG clock periods from

zero up to the value in the blanking count register. Use

Equation 11-1 to calculate blanking times.

11.6.1

RISING EDGE INPUT BLANKING

The falling edge blanking counter inhibits the rising

edge input from triggering a rising edge event. The

falling edge blanking time starts when the falling edge

output drive goes true.

The falling edge blanking time is set by the value con-

tained in the GxBLKF<3:0> bits of the COGxBLK reg-

ister. Blanking times are calculated using the formula

shown in Equation 11-1.

When the GxBLKF<3:0> value is zero, falling edge

blanking is disabled and the blanking counter output is

true, thereby, allowing the event signal to pass straight

through to the event trigger circuit.

11.6.2

FALLING EDGE INPUT BLANKING

Rising edge blanking inhibits the falling edge input

from triggering a falling edge event. The rising edge

blanking time starts when the rising edge output drive

goes true.

The rising edge blanking time is set by the value

contained in the GxBLKR<3:0> bits of the COGxBLK

When the GxBLKR<3:0> value is zero, rising edge

blanking is disabled and the blanking counter output is

true, thereby, allowing the event signal to pass straight

through to the event trigger circuit.

11.6.3

BLANKING TIME UNCERTAINTY

When the rising and falling edge events that trigger the

blanking counters are asynchronous to the COG

clock, it creates uncertainty in the blanking time. The

maximum uncertainty is equal to one COG clock

period. Refer to Equation 11-1 and Example 11-1 for

more detail.

11.7

Phase Delay

It is possible to delay the assertion of the rising edge

event. This is accomplished by placing a non-zero

value in COGxPH register. Refer to Register 11-6 and

Figure 11-3 for COG operation with CCP1 and phase

delay. The delay from the input rising edge signal

switching to the actual assertion of the events is calcu-

lated the same as the dead-band and blanking delays.

Please see Equation 11-1.

11.7.1

CUMULATIVE UNCERTAINTY

It is not possible to create more than one COG clock of

uncertainty by successive stages. Consider that the

phase delay stage comes after the blanking stage, the

dead-band stage comes after either the blanking or

phase delay stages, and the blanking stage comes

after the dead-band stage. When the preceding stage

is enabled, the output of that stage is necessarily

synchronous with the COG, which removes any

possibility of uncertainty in the succeeding stage.

EQUATION 11-1:

PHASE, DEAD-BAND,

AND BLANKING TIME

CALCULATION

min

Count

max

Count

COG_clock

--------------------------

uncertainty

max

min

–

uncertainty

COG_clock

--------------------------

Also:

Where:

Count

Phase Delay

GxPH<3:0>

Rising Dead Band

GxDBR<3:0>

Falling Dead Band

GxDBF<3:0>

Rising Event Blanking

GxBLKR<3:0>

Falling Event Blanking

GxBLKF<3:0>

COG_clock

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