PIC12F752 datasheet(86/204 Pages) MICROCHIP

86 / 204 page

PIC12F752/HV752

DS41576A-page 86

Preliminary

 2011 Microchip Technology Inc.

11.4

Output Control

Immediately after the COG module is enabled, the

complementary

drive

configured

with

both

COGxOUT0 and COGxOUT1 drives cleared.

11.4.1

OUTPUT ENABLES

Each COG output pin has individual output enable

control. Output enables are selected with the GxOE0

and GxOE1 bits of the COGxCON0 register. When an

output enable control is cleared, the module asserts

no control over the pin. When an output enable is set,

the override value or active PWM waveform is applied

to the pin per the port priority selection.

The output pin enables are dependent on the module

enable bit, GxEN. When GxEN is cleared, COG output

enables and COG drive levels have no effect.

11.4.2

POLARITY CONTROL

The polarity of each COG output can be selected

independently. When the output polarity bit is set, the

corresponding output is active low. Clearing the output

polarity bit configures the corresponding output as

active high. However, polarity does not affect the

override levels.

Output polarity is selected with the GxPOL0 and

GxPOL1 bits of the COGxCON0 register.

11.5

Dead-Band Control

The dead-band control provides for non-overlapping

PWM output signals to prevent shoot through current

in the power switches.

The COG contains two 4-bit dead-band counters. One

dead-band counter is used for rising edge dead-band

control. The other is used for falling edge dead-band

control.

Dead band is timed by counting COG clock periods

from zero up to the value in the dead-band count

times.

11.5.1

RISING EDGE DEAD BAND

Rising

edge

dead-band

delays

the

turn-on

COGxOUT0 from when COGxOUT1 is turned off. The

rising edge dead-band time starts when the rising

edge output goes true.

The rising edge output into the dead-band counter

may be delayed by the phase delay. When the phase

delay time is zero, the rising edge output goes true

coincident with the unblanked rising edge input event.

When the phase delay time is not zero, the rising edge

output goes true at the completion of the phase delay

time.

The rising edge dead-band time is set by the value

contained in the GxDBR<3:0> bits of the COGxDB

band is disabled.

11.5.2

FALLING EDGE DEAD BAND

Falling

edge

dead-band

delays

the

turn-on

COGxOUT1 from when COGxOUT0 is turned off. The

falling edge dead-band time starts when the falling

edge output goes true. The falling edge output goes

true coincident with the unblanked falling edge input

event.

The falling edge dead-band time is set by the value

contained in the GxDBF<3:0> bits of the COGxDB

band is disabled.

11.5.3

DEAD-BAND TIME UNCERTAINTY

When the rising and falling edge events that trigger the

dead-band counters come from asynchronous inputs,

it creates uncertainty in the dead-band time. The max-

imum uncertainty is equal to one COG clock period.

Refer to Equation 11-1 for more detail.

11.5.4

DEAD-BAND OVERLAP

There are two cases of dead-band overlap:

• Rising-to-falling

• Falling-to-rising

11.5.4.1

Rising-to-Falling Overlap

In this case, the falling edge event occurs while the ris-

ing edge dead-band counter is still counting. When

this happens, the COGxOUT0 drive is suppressed and

the dead band extends by the falling edge dead-band

time. At the termination of the extended dead-band

time, the COGxOUT1 drive goes true.

11.5.4.2

Falling-to-Rising Overlap

In this case, the rising edge event occurs while the fall-

ing edge dead-band counter is still counting. When

this happens, the COGxOUT1 drive is suppressed and

the dead band extends by the rising edge dead-band

time. At the termination of the extended dead-band

time, the COGxOUT0 drive goes true.

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