©2011 Silicon Storage Technology, Inc.

S71296-05-000

02/11

11

8 Mbit SPI Serial Flash

SST25VF080B

Data Sheet

A Microchip Technology Company

High-Speed-Read (66/80 MHz)

The High-Speed-Read instruction supporting up to 66 MHz (for SST25VF080B-50-xx-xxxx) or 80 MHz

(for SST25VF040B-80-xx-xxxx) Read is initiated by executing an 8-bit command, 0BH, followed by

address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-

Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.

Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-

fied address location. The data output stream is continuous through all addresses until terminated by a

low to high transition on CE#. The internal address pointer will automatically increment until the high-

est memory address is reached. Once the highest memory address is reached, the address pointer

will automatically increment to the beginning (wrap-around) of the address space. Once the data from

address location FFFFFH has been read, the next output will be from address location 00000H.

Figure 6: High-Speed-Read Sequence

1296 HSRdSeq.0

CE#

SO

SI

SCK

ADD.

012 34 5

6 7 8

ADD.

ADD.

0B

HIGH IMPEDANCE

15 16

23 24

31 32

39 40

47 48

55 56

63 64

N+2

N+3

N+4

N

N+1

X

MSB

MSB

MSB

MODE 0

MODE 3

80

71 72