MCP3301 datasheet(18/38 Pages) MICROCHIP

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MCP3301

DS21700D-page 18

 2011 Microchip Technology Inc.

FIGURE 5-3:

Analog Input Model.

5.2.1

MAINTAINING MINIMUM CLOCK

SPEED

When the MCP3301 initiates, charge is stored on the

sample capacitor. When the sample period is complete,

the device converts one bit for each clock that is

received. It is important for the user to note that a slow

clock rate will allow charge to bleed off the sample

capacitor while the conversion is taking place. For

MCP3301 devices, the recommended minimum clock

speed during the conversion cycle (tCONV) is 85 kHz.

Failure to meet this criteria may introduce linearity

errors into the conversion outside the rated specifica-

tions. It should be noted that, during the entire conver-

sion

cycle,

the

A/D

converter

does

not

have

requirements for clock speed or duty cycle, as long as

all timing specifications are met.

5.3

Biasing Solutions

For pseudo-differential bipolar operation, the biasing

circuit shown in Figure 5-4 shows a single-ended input

AC coupled to the converter. This configuration will give

a digital output range of -4096 to +4095. With the 2.5V

reference, the LSB size is equal to 610 µV.

Although the ADC is not production tested with a 2.5V

reference as shown, linearity will not change more than

0.1 LSB. See Figure 2-2 and Figure 2-6 for INL and

DNL errors versus VREF at VDD = 5V. A trade-off exists

between the high-pass corner and the acquisition time.

The value of C will need to be quite large in order to

bring down the high-pass corner. The value of R needs

to be 1 k

 or less, since higher input impedances

require additional acquisition time.

Using the values in Figure 5-4, we have a 100 Hz cor-

ner frequency. See Figure 5-2 for the relationship

between input impedance and acquisition time.

FIGURE 5-4:

Pseudo-differential biasing

circuit for bipolar operation.

CPIN

CHx

7pF

VT = 0.6V

ILEAKAGE

Sampling

Switch

RSS = 1 k

CSAMPLE

= DAC capacitance

VSS

VDD

= 25 pF

±1 nA

Legend

signal source

source impedance

CHx

input channel pad

CPIN

input pin capacitance

threshold voltage

ILEAKAGE

leakage current at the pin due to various junctions

sampling switch

RSS

sampling switch resistor

CSAMPLE

sample/hold capacitance

VDD = 5V

0.1 µF

IN+

IN-

VREF

MCP3301

1µF

MCP1525

VIN

VOUT

0.1 µF



10 µF

VIN

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