MCP4726 datasheet(39/86 Pages) MICROCHIP

39 / 86 page

DS22272A-page 39

MCP4706/4716/4726

4.5

Power-Down Operation

To allow the application to conserve power when the

DAC operation is not required, three power down

modes are available. The Power-Down configuration

bits (PD1:PD0) control the power down operation

(Figure 4-5). All power down modes do the following:

• Turning off most of its internal circuits (op amp,

resistor ladder, ...)

• Op amp output becomes high impedance to the

VOUT pin

• Disconnects resistor ladder from reference

voltage (VRL)

• Retains the value of the volatile DAC register and

configuration bits, and the nonvolatile (EEPROM)

DAC register and configuration bits

Depending on the selected power down mode, the

following will occur:

•VOUT pin is switched to one of three resistive pull

downs (See Table 4-2)

- 640k

Ω (typical)

- 125k

Ω (typical)

-1k

Ω (typical)

There is a delay (TPDE) between the PD1:PD0 bits

changing from ‘00’ to either ‘01’, ‘10’, or ‘11’ and the op

amp no longer driving the VOUT output and the pull

down resistors are sinking current.

In any of the power down modes, where the VOUT pin

is not externally connected (sinking or sourcing

current), the power down current will typical be 60 nA

(see Section 1.0 “Electrical Characteristics”).

Section 6.0 “MCP47X6 I2C Commands” describes

the I2C commands for writing the power-down bits. The

commands that can update the volatile PD1:PD0 bits

are:

• Write Volatile DAC Register

• Write Volatile Memory

• Write All Memory

• Write Volatile Configuration bits

• General Call Reset

• General Call Wake-up

TABLE 4-2:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

FIGURE 4-5:

Op Amp to VOUT Pin Block

Diagram.

4.5.1

EXITING POWER-DOWN

When the device exits the power down mode the

following occurs:

• Disabled circuits (op amp, resistor ladder, ...) are

turned on

• Resistor ladder is connected to selected

reference voltage (VRL)

• Selected pull down resistor is disconnected

•The VOUT output will be driven to the voltage

represented by the volatile DAC Register’s value

and configuration bits

The VOUT output signal will require time as these

circuits are powered up and the output voltage is driven

to the specified value as determined by the volatile

DAC register and configuration bits.

The following events will change the PD1:PD0 bits to

‘00’ and therefore exit the Power-Down mode. These

are:

•Any I2C write command for where the PD1:PD0

bits are ‘00’.

•I2C General Call Wake-up Command.

•I2C General Call Reset Command.

(if nonvolatile PD1:PD0 bits are ‘00’).

Note:

The I2C serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

I2C master device.

PD1

PD0

Function

Normal operation

Ω resistor to ground

125 k

Ω resistor to ground

640 k

Ω resistor to ground

Note:

Since the op amp and resistor ladder were

powered off (0V), the op amp’s input

voltage (VW) can be considered 0V. There

is a delay (TPDD) between the PD1:PD0

bits updated to ‘00’ and the op amp driving

the VOUT output. The op amp’s settling

time (from 0V) needs to be taken into

account to ensure the VOUT voltage

reflects the selected value.

VOUT

PD1:PD0

Amp

Gain (1x or 2x)

(Gx = 0 or 1)

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