33894 datasheet(20/28 Pages) FREESCALE

20 / 28 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33894

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DEVICE REGISTER ADDRESSING

The following section describes the possible register

addresses and their impact on device operation.

ADDRESS XX000—STATUS REGISTER (STATR)

The STATR register is used to read the device status and

the various configuration register contents without disrupting

the device operation or the register contents. The register bits

D4:D0 determine the content of the first sixteen bits of SO

data. In addition to the device status, this feature provides the

ability to read the content of the OCR0, OCR1, SOCHLR,

CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to

the section entitled Serial Output Communication (Device

Status Return Data) beginning on page 22.)

ADDRESS X0001—OUTPUT CONTROL REGISTER

(OCR0)

The OCR0 register allows the MCU to control the ON/OFF

state of four outputs through the SPI. Incoming message bit

D3:D0 reflects the desired states of the four high-side

outputs (INx_SPI), respectively. A logic [1] enables the

corresponding output switch and a logic [0] turns it OFF.

ADDRESS X1001—OUTPUT CONTROL REGISTER

(OCR1)

Incoming message bits D3:D0 reflect the desired output

that will be mirrored on the Current Sense (CSNS) pin. A

logic [1] on message bits D3:D0 enables the CSNS pin for

outputs HS3:HS0, respectively. In the event the current

sense is enabled for multiple outputs, the current will be

summed. In the event that bits D3:D0 are all logic [0], the

output CSNS will be tri-stated. This is useful when several

CSNS pins of several devices share the same A/D converter.

ADDRESS A1A0010—SELECT OVERCURRENT

HIGH AND LOW REGISTER (SOCHLR_S)

The SOCHLR_s register allows the MCU to configure the

output overcurrent low and high detection levels,

respectively. Each output “s” is independently selected for

configuration based on the state of the D12:D11 bits

(Table 9).

Each output can be configured to different levels. In

addition to protecting the device, this slow blow fuse

emulation feature can be used to optimize the load

requirements matching system characteristics. Bits D2:D0

set the overcurrent low detection level to one of eight possible

levels, as shown in Table 10, page 21. Bit D3 sets the

overcurrent high detection level to one of two levels, as

outlined in Table 11, page 21.

Table 8. Serial Input Address and Configuration Bit Map

SI Register

SI Data

D15

D14 D13 D12 D11 D10

STATR

WDIN

SOA4

SOA3

SOA2

SOA1

SOA0

OCR0

WDIN

IN3_SPI

IN2_SPI

IN1_SPI

IN0_SPI

OCR1

WDIN

CSNS3 EN

CSNS2 EN

CSNS1 EN CSNS0 EN

SOCHLR_s

WDIN

SOCH_s

SOCL2_s

SOCL1_s

SOCL0_s

CDTOLR_s

WDIN

OL_DIS_s

OCL_DIS_s

OCLT1_s

OCLT0_s

DICR_s

WDIN

FAST_SR_s CSNS_high_

DIR_DIS_s

A/O_s

UOVR

WDIN

UV_DIS

OV_DIS

WDR

WDIN

WD1

WD0

NAR

WDIN

No Action (Allow Toggling of D15–WDIN)

TEST

WDIN

Freescale Internal Use (Test)

x=Don’t care.

s=Output selection with the bits A1A0 as defined in Table 9.

Table 9. Output Selection

A1 (D12)

A0 (D11)

HS_s

HS0

HS1

HS2

HS3

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